AD9558 datasheet(67/104 Pages) AD

67 / 104 page

Data Sheet

AD9558

Rev. A | Page 67 of 104

Reg

Addr

(Hex)

Opt

Name

Def

Profile C (for REFC)

0x0780

Reference

period (up to

1.1 ms)

Nominal period (fs), Bits[7:0] (default: 125 μs = 1/(8 kHz) for default system clock setting)

0x0781

Nominal period (fs), Bits[15:8]

0x0782

Nominal period (fs), Bits[23:16]

0x0783

Nominal period (fs), Bits[31:24]

0x0784

Nominal period (fs), Bits[39:32]

0x0785

Frequency

tolerance

Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)

0x0786

Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)

0x0787

Reserved

Inner tolerance, Bits[19:16]

0x0788

Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm] (default: 10%)

0x0789

Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)

0x078A

Reserved

Outer tolerance, Bits[19:16]

0x078B

Validation

Validation timer (ms), Bits[7:0] (up to 65.5 seconds)

0x078C

Validation timer (ms), Bits[15:8] (up to 65.5 seconds)

0x078D

Reserved

0x078E

Select base

loop filter

Reserved

Sel high PM

base loop filt

0x078F

DPLL loop BW

Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz)

0x0790

Digital PLL loop BW scaling factor[15:8]

0x0791

Reserved

BW scaling

factor[16]

0x0792

DPLL

R divider

(20 bits)

R divider[7:0]

0x0793

R divider[15:8]

0x0794

Reserved

Enable REFC

divide-by-2

R divider[19:16]

0x0795

DPLL

N divider

(17 bits)

Digital PLL feedback divider—Integer Part N1[7:0]

0x0796

Digital PLL feedback divider—Integer Part N1[15:8]

0x0797

Reserved

Digital PLL

feedback

divider—

Integer Part

N1[16]

0x0798

DPLL

fractional

feedback

divider

(24 bits)

Digital PLL fractional feedback divider—FRAC1[7:0]

0x0799

Digital PLL fractional feedback divider—FRAC1[15:8]

0x079A

Digital PLL fractional feedback divider—FRAC1[23:16]

0x079B

DPLL

fractional

feedback

divider

modulus

(24 bits)

Digital PLL feedback divider modulus—MOD1[7:0]

0x079C

Digital PLL feedback divider modulus—MOD1[15:8]

0x079D

Digital PLL feedback divider modulus—MOD1[23:16]

0x079E

Lock detectors

Phase lock threshold (ps), Bits[7:0]

0x079F

Phase lock threshold (ps), Bits[15:8]

0x07A0

Phase lock fill rate[7:0]

0x07A1

Phase lock drain rate[7:0]

0x07A2

Frequency lock threshold[7:0]

0x07A3

Frequency lock threshold[15:8]

0x07A4

Frequency lock threshold[23:16]

0x07A5

Frequency lock fill rate[7:0]

0x07A6

Frequency lock drain rate[7:0]

AD9558 Datasheet(PDF) 67 Page - Analog Devices

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