AD9558 datasheet(68/104 Pages) AD

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AD9558

Data Sheet

Rev. A | Page 68 of 104

Reg

Addr

(Hex)

Opt

Name

Def

DPLL Profile D (for REFD)

0x07C0

Reference

period (up to

1.1 ms)

Nominal reference period (fs), Bits[7:0] (default: 51.44 ns =1/(19.44 MHz) for default system clock setting)

0x07C1

Nominal period (fs), Bits[15:8]

0x07C2

Nominal period (fs), Bits[23:16]

0x07C3

Nominal period (fs), Bits[31:24]

0x07C4

Nominal period (fs), Bits[39:32]

0x07C5

Tolerance

Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)

0x07C6

Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)

0x07C7

Reserved

Inner tolerance, Bits[19:16]

0x07C8

Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm) (default: 10%)

0x07C9

Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)

0x07CA

Reserved

Outer tolerance, Bits[19:16]

0x07CB

Validation

Validation timer (ms), Bits[7:0] (up to 65.5 seconds)

0x07CC

Validation timer (ms), Bits[15:8] (up to 65.5 seconds]

0x07CD

Reserved

0x07CE

Select base

loop filter

Reserved

Sel high PM

base loop

filter

0x07CF

DPLL loop BW

Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz)

0x07D0

Digital PLL loop bandwidth BW scaling factor[15:8]

0x07D1

Reserved

BW scaling

factor[16]

0x07D2

DPLL

R divider

(20 bits)

R divider[7:0]

0x07D3

R divider[15:8]

0x07D4

Reserved

Enable

REFD

divide-by-2

R divider[19:16]

0x07D5

DPLL

N divider

(17 bits)

Digital PLL feedback divider—Integer Part N1[7:0]

0x07D6

Digital PLL feedback divider—Integer Part N1[15:8]

0x07D7

Reserved

Digital PLL

feedback

divider—

Integer Part

N1[16]

0x07D8

DPLL

fractional

feedback

divider

(24 bits)

Digital PLL fractional feedback divider—FRAC1[7:0]

0x07D9

Digital PLL fractional feedback divider—FRAC1[15:8]

0x07DA

Digital PLL fractional feedback divider—FRAC1[23:16]

0x07DB

DPLL

fractional

feedback

divider

modulus

(24 bits)

Digital PLL feedback divider modulus—MOD1[7:0]

0x07DC

Digital PLL feedback divider modulus—MOD1[15:8]

0x07DD

Digital PLL feedback divider modulus—MOD1[23:16]

0x07DE

Lock detectors

Phase lock threshold (ps), Bits[7:0]

0x07DF

Phase lock threshold(ps), Bits[15:8]

0x07E0

Phase lock fill rate[7:0]

0x07E1

Phase lock drain rate[7:0]

0x07E2

Frequency lock threshold[7:0]

0x07E3

Frequency lock threshold[15:8]

0x07E4

Frequency lock threshold[23:16]

0x07E5

Frequency lock fill rate[7:0]

0x07E6

Frequency lock drain rate[7:0]

AD9558 Datasheet(PDF) 68 Page - Analog Devices

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