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AD9558 Datasheet(PDF) 3 Page - Analog Devices |
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AD9558 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 104 page  Data Sheet AD9558 Rev. A | Page 3 of 104 Register Map Bit Descriptions.......................................................72 Serial Port Configuration (Register 0x0000 to Register 0x0005)..........................................................................72 Silicon Revision (Register 0x000A) ..........................................72 Clock Part Serial ID (Register 0x000C to Register 0x000D).72 System Clock (Register 0x0100 to Register 0x0108) ..............73 General Configuration (Register 0x0200 to Register 0x0214)..........................................................................74 IRQ Mask (Register 0x020A to Register 0x020F)...................75 DPLL Configuration (Register 0x0300 to Register 0x032E) .76 Output PLL Configuration (Register 0x0400 to Register 0x0408)..........................................................................79 Output Clock Distribution (Register 0x0500 to Register 0x0515)..........................................................................81 Reference Inputs (Register 0x0500 to Register 0x0507) ........85 Frame Synchronization (Register 0x0640 to Register 0x0641)..........................................................................86 DPLL Profile Registers (Register 0x0700 to Register 0x07E6) .........................................................................87 Operational Controls (Register 0x0A00 to Register 0x0A10).........................................................................89 Quick In/Out Frequency Soft Pin Configuration (Register 0x0C00 to Register 0x0C08) .....................................92 Status ReadBack (Register 0x0D00 to Register 0x0D14).......93 EEPROM Control (Register 0x0E00 to Register 0x0E03) .....97 EEPROM Storage Sequences (Register 0x0E10 to Register 0x0E3C).........................................................................98 Outline Dimensions......................................................................104 Ordering Guide .........................................................................104 REVISION HISTORY 4/12—Rev 0 to Rev. A Changed 3 Hz to 352 kHz in Output Frequencies List Item, Features Section................................................................................. 1 Change to Output Frequency Range Parameter, Min; and System Clock Input Doubler Duty Cycle Parameter Description, Table 6... 6 Changes to Test Conditions/Comments Column, Table 9 .......... 8 Changes to Output Frequency Parameters, Min, Table 10 .......... 9 Changes to Pin 4 and Pin 42, Table 20 ......................................... 17 Changes to Device Register Programming When Using a Register Setup File and Register Programming Overview Sections............................................................................................. 26 Changed APLL VCO Lower Frequency and OUT5 Frequency Range, Figure 35; Changed 225 MHz to 200 MHz and 3.45 GHz to 3.35 GHz in Overview Section................................................... 29 Changes to Reference Profiles Section ......................................... 30 Changes to Programmable Digital Loop Filter Section ............. 32 Changes to System Clock Inputs Section..................................... 35 Changes to Output PLL (APLL) Section; Changes to Figure 39 .... 37 Changes to Figure 40; Changed 1024 to 1023 in Clock Dividers Section; Changes to Clock Distribution Synchronization Section .............................................................................................. 38 Changes to Multifunction Pins (M7 to M0) and IRQ Pin Sections............................................................................................. 42 Changes to Figure 44 ...................................................................... 43 Changes to EEPROM Conditional Processing Section and Figure 45............................................................................................ 46 Added Programming the EEPROM to Configure an M Pin to Control Synchronization of Clock Distribution Section ......... 48 Changes to the Power Supply Partitions Section ........................ 58 Changed 89.5° to 88.5° in DPLL Phase Margin Section ............ 59 Changes to Address 0x0006, Address 0x0007, and Address 0x000A, Table 35 .............................................................. 62 Changes to Address 0x0304, Table 35 .......................................... 63 Changes to Address 0x0405, Table 35 .......................................... 64 Changes to Address 0x071A and Address 0x071D, Table 35 .... 65 Changes to Address 0x0780, Address 0x0785 to Address 0x078A, Address 0x079A, Address 0x079D, Table 35 ... 67 Changes to Address 0x07C0, Address 0x07DA, and Address 0x07DD, Table 35............................................................. 68 Change to Address 0x0A01, Bit 7, Table 35................................. 69 Added Address 0x0E3D to Address 0x0E45, Table 35............... 71 Change to Table 38; Added Table 40, Renumbered Sequentially; Changes to Table 41 ........................................................................ 72 Change to Bit 0, Address 0x0101, Table 43.................................. 73 Changes to Address 0x0304, Table 55 .......................................... 76 Deleted Address 0x0305, Table 55 ................................................ 76 Changes to Table Title, Table 63; Changes to Address 0x0400 and Address 0x0403, Table 64........................................................ 79 Changes to Address 0x0405, Table 64 .......................................... 80 Changes to Descriptions, Address 0x0500, Table 67.................. 81 Changes to Bit 0, Address 0x0501, Table 68 ................................ 82 Changes to Bits[6:4], Address 0x0505 and Changes to Address 0x0506, Table 70............................................................... 83 Changes to Bits[6:4] and Bit 0, Address 0x050F, Table 73 ......... 84 Change to Address 0x0704, Table 78; Changes to Bits[3:0] in Address 0x0707 and Address 070A, Table 79; and Changes to Address 0x070E, Table 82................................................................ 87 Changes to Address 0x0710, Table 83; and Changes to Bits[3:0], Address 0x0714, Table 84 ................................................................. 88 Changes to Bits[1:0], Address 0x0A01, Table 90........................... 89 Changes to Descriptions, Address 0x0A0B, Table 99................. 91 Changes to Bit 4, Address 0x0C06, Table 100 ............................. 93 Changes to Bit 6 and Bit 1, Address 0x0D01, Table 102 ............ 94 Changes to Table Summary, Table 114......................................... 98 Added Table 128............................................................................ 101 Changes to Table 129 .................................................................... 102 Changes to Table 130 .................................................................... 103 10/11—Revision 0: Initial Version |
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