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AD9558 Datasheet(PDF) 98 Page - Analog Devices |
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AD9558 Datasheet(HTML) 98 Page - Analog Devices |
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98 / 104 page  AD9558 Data Sheet Rev. A | Page 98 of 104 EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3C) The default settings of Register 0x0E10 to Register 0x0E3C contain the default EEPROM instruction sequence. The tables in this section provide descriptions of the register defaults, based on the assumption that the controller has been instructed to carry out an EEPROM storage sequence in which all of the registers are stored and loaded by the EEPROM. Table 114. EEPROM Storage Sequence for System Clock Settings Address Bits Bit Name Description 0x0E10 [7:0] The default value of this register is 0x01, which the controller interprets as a data instruction. Its decimal value is 1, so this tells the controller to transfer two bytes of data (1 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x01 in the EEPROM and increments the EEPROM address pointer. 0x0E11 [7:0] 0x0E12 [7:0] EEPROM ID The default value of these two registers is 0x0006. Note that Register 0x0E11 and Register 0x0E12 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0006). The controller stores 0x0006 in the EEPROM and increments the EEPROM pointer by 2. It then transfers two bytes from the register map (beginning at Address 0x0006) to the EEPROM and increments the EEPROM address pointer by 3 (two data bytes and one checksum byte). The two bytes transferred correspond to the system clock parameters in the register map. 0x0E13 [7:0] The default value of this register is 0x08, which the controller interprets as a data instruction. Its decimal value is 8, so this tells the controller to transfer nine bytes of data (8 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments the EEPROM address pointer. 0x0E14 [7:0] 0x0E15 [7:0] System clock The default value of these two registers is 0x0100. Note that Register 0x0E14 and Register 0x0E15 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0100). The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then transfers nine bytes from the register map (beginning at Address 0x0100) to the EEPROM and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine bytes transferred correspond to the system clock parameters in the register map. 0x0E16 [7:0] I/O update The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. Table 115. EEPROM Storage Sequence for General Configuration Settings Address Bits Bit Name Description 0x0E17 [7:0] General The default value of this register is 0x11, which the controller interprets as a data instruction. Its decimal value is 17, which tells the controller to transfer 18 bytes of data (17 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x11 in the EEPROM and increments the EEPROM address pointer. 0x0E18 [7:0] 0x0E19 [7:0] The default value of these two registers is 0x0200. Note that Register 0x0E18 and Register 0x0E19 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0200). The controller stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 18 bytes from the register map (beginning at Address 0x0200) to the EEPROM and increments the EEPROM address pointer by 19 (18 data bytes and one checksum byte). The 18 bytes transferred correspond to the general configuration parameters in the register map. Table 116. EEPROM Storage Sequence for DPLL Settings Address Bits Bit Name Description 0x0E1A [7:0] DPLL The default value of this register is 0x2E, which the controller interprets as a data instruction. Its decimal value is 46, which tells the controller to transfer 47 bytes of data (46 + 1), beginning at the address that is specified by the next two bytes. The controller stores 0x2E in the EEPROM and increments the EEPROM address pointer. 0x0E1B [7:0] 0x0E1C [7:0] The default value of these two registers is 0x03. Note that Register 0x0E1B and Register 0x0E1C are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0300). The controller stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 47 bytes from the register map (beginning at Address 0x0300) to the EEPROM and increments the EEPROM address pointer by 48 (47 data bytes and one checksum byte). The 47 bytes transferred correspond to the DPLL parameters in the register map. |
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