AD9558 datasheet(74/104 Pages) AD

74 / 104 page

AD9558

Data Sheet

Rev. A | Page 74 of 104

GENERAL CONFIGURATION (REGISTER 0x0200 TO REGISTER 0x0214)

Multifunction Pin Control (M0 to M7) and IRQ Pin Control (Register 0x0200 to Register 0x0209)

Note that the default setting for the M0 to M5 multifunction pins and the IRQ is that of a 3-level logic input; M6 and M7 are unused inputs at

startup. After startup, M0 to M7 are 2-level inputs or 2-level outputs, based on the settings of Register 0x0200 to Register 0x0208. Setting

Bit 0 in Register 0x0200 to 1 enables M0 to M7 pin functionality.

Table 46. Multifunction Pin (M0 to M7) Control

Address

Bits

Bit Name

Description

[7:1]

Reserved

Reserved.

0x0200

Enable M pins and IRQ pin

function

0 (default) = disables the function of the M pins and IRQ pin control register (Address

0x0201 to Address 0x0209) and the M pins and IRQ pin are in 3-level logic input state.

1 = the M pins and IRQ pin are out of 3-level logic input state. Enables the function of the

M pins and IRQ pin control register (Address 0x0201 to Address 0x0209).

M0 output/input

In/out control for M0 pin.

0 = input (2-level logic control pin).

1 (default) = output (2-level logic status pin).

0x0201

[6:0]

M0 function

See Table 129 and Table 130. Default: 0xB0 = REFA valid.

M1 output/input

In/out control for M1 pin (same as M0).

0x0202

[6:0]

M1 function

See Table 129 and Table 130. Default: 0xB1 = REFB valid.

M2 output/input

In/out control for M2 pin (same as M0).

0x0203

[6:0]

M2 function

See Table 129 and Table 130. Default: 0xC0 = REFA active.

M3 output/input