AD9558 datasheet(31/104 Pages) AD

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Data Sheet

AD9558

Rev. A | Page 31 of 104

In the automatic modes, a fully automatic priority-based algorithm

selects which reference is the active reference. When programmed

for an automatic mode, the device chooses the highest priority

valid reference. When both references have the same priority,

REFA gets preference over REFB. However, the reference position

is used only as a tie-breaker and does not initiate a reference switch.

The following list gives an overview of the five operating modes:

•

Automatic revertive mode. The device selects the highest

priority valid reference and switches to a higher priority

reference if it becomes available, even if the reference in use

is still valid. In this mode, the user reference is ignored.

•

Automatic non-revertive mode. The device stays with the

currently selected reference as long as it is valid, even if

a higher priority reference becomes available. The user

reference is ignored in this mode.

•

Manual with automatic fallback mode. The device uses the

user reference for as long as it is valid. If it becomes invalid,

the reference input with the highest priority is chosen in

accordance with the priority-based algorithm.

•

Manual with holdover mode. The user reference is the

active reference until it becomes invalid. At that point,

the device automatically goes into holdover.

•

Manual mode without holdover. The user reference is the

active reference, regardless of whether or not it is valid.

The user also has the option to force the device directly into

holdover or free run operation via the user holdover and user

freerun bits. In free run mode, the free run frequency tuning

word register defines the free run output frequency. In holdover

mode, the output frequency depends on the holdover control

settings (see the Holdover section).

Phase Build-Out Reference Switching

The AD9558 supports phase build-out reference switching,

which is the term given to a reference switchover that

completely masks any phase difference between the previous

reference and the new reference. That is, there is virtually no

phase change detectable at the output when a phase build-out

switchover occurs.

DIGITAL PLL (DPLL) CORE

DPLL Overview

DIGITAL

LOOP

FILTER

÷N1

R DIVIDER

(20-BIT)

24-BIT/24-BIT

RESOLUTION

FRAC1/

MOD1

17-BIT

INTEGER

TUNING

WORD

CLAMP

AND

HISTORY

×2

FREE RUN

SYSTEM

CLOCK

FROM APLL

FROM

REF

INPUT

MUX

TO APLL

Figure 36. Digital PLL Core

A diagram of the DPLL core of the AD9558 appears in Figure 36.

The phase/frequency detector, feedback path, lock detectors,

phase offset, and phase slew rate limiting that comprise this

second generation DPLL are all digital implementations.

The start of the DPLL signal chain is the reference signal, fR,

which is the frequency of the reference input. A reference

prescaler reduces the frequency of this signal by an integer factor,

R + 1, where R is the 20-bit value stored in the appropriate

profile register and 0 ≤ R ≤ 1,048,575. Therefore, the frequency

at the output of the R-divider (or the input to the time-to-digital

converter (TDC)) is

TDC

A TDC samples the output of the R-divider. The TDC/PFD

produces a time series of digital words and delivers them to the

digital loop filter. The digital loop filter offers the following

advantages:

•

Determination of the filter response by numeric

coefficients rather than by discrete component values

•

The absence of analog components (R/L/C), which

eliminates tolerance variations due to aging

•

The absence of thermal noise associated with analog

components

•

The absence of control node leakage current associated

with analog components (a source of reference feed-

through spurs in the output spectrum of a traditional

analog PLL)

The digital loop filter produces a time series of digital words at

its output and delivers them to the frequency tuning input of a

sigma-delta (Σ-Δ) modulator (SDM). The digital words from

the loop filter steer the DCO frequency toward frequency and

phase lock with the input signal (fTDC).

The DPLL includes a feedback divider that causes the digital

loop to operate at an integer-plus-fractional multiple. The

output of the DPLL is

⎥⎦

⎤

⎢⎣

⎡

MOD1

FRAC1

TDC

DPLL

OUT

)

(

where N1 is the 17-bit value stored in the appropriate profile

registers (Register 0x0715 to Register 0x0717 for REFA). FRAC1

and MOD1 are the 24-bit numerators and denominators of the

fractional feedback divider block. The fractional portion of the

feedback divider can be bypassed by setting FRAC1 to 0, but

MOD1 should never be 0.

The DPLL output frequency is usually 175 MHz to 200 MHz for

optimal performance.

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