 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9558 Datasheet(PDF) 59 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9558 Datasheet(HTML) 59 Page - Analog Devices |
|
|
59 / 104 page  Data Sheet AD9558 Rev. A | Page 59 of 104 PIN PROGRAM FUNCTION DESCRIPTION The AD9558 supports both hard pin and soft pin program function with the on-chip ROM containing the predefined configurations. When a pin program function is enabled and initiated, the selected predefined configuration is transferred from the ROM to the corresponding registers to configure the part into the desired state. OVERVIEW OF ON-CHIP ROM FEATURES Input/Output Frequency Translation Configuration The AD9558 has one on-chip ROM that contains a total of 256 different input-output frequency translation configurations for independent selection of 16 input frequencies and 16 output frequencies. Each input/output frequency translation configuration assumes that all input frequencies are the same and all the output frequencies are the same. Each configuration reprograms the following registers/parameters: • Reference input period register • Reference divider R register • Digital PLL feedback divider register (Fractional Part FRAC1, Modulus Part MOD1 and Integer Part N1) free run • Tuning word register • Output PLL feedback divider N2 register • RF divider register • Clock distribution channel divider register All configurations are set to support one single system clock frequency as 786.432 MHz (16× the default 49.152 MHz system clock reference frequency). Four Different System Clock PLL Configurations • REF = 49.152 MHz XO (×2 on, N = 8) • REF = 49.152 MHz XTAL (×2 on, N = 8) • REF = 24.756 MHz XTAL (×2 on, N = 16) • REF = 98.304 MHz XO (×2 off, N = 8) Four Different DPLL Loop Bandwidths • 1 Hz, 10 Hz, 50 Hz, 100 Hz DPLL Phase Margin • Normal phase margin (70°) • High phase margin (88.5°) The ROM also contains an APLL VCO calibration bit. This bit is used to program Register 0x0405[0] (from 0) to 1 to generate a low-high transition to automatically initiate APLL VCO cal. Table 32. Preset Input Frequencies for Hard Pin and Soft Pin Programming Hard Pin Program PINCONTROL = High Soft Pin Program PINCONTROL = Low Register 0x0C01[3:0] Freq ID Frequency (MHz) Frequency Description M5 Pin M4 Pin M0 Pin B3 B2 B1 B0 0 0.008 8 kHz 0 0 0 0 0 0 0 1 19.44 19.44 MHz 0 0 ½ 0 0 0 1 2 25 25 MHz 0 0 1 0 0 1 0 3 125 125 MHz 0 ½ 0 0 0 1 1 4 156.7072 156..25 MHz × 1027/1024 0 ½ ½ 0 1 0 0 5 622.08 622.08 MHz 0 ½ 1 0 1 0 1 6 625 625 MHz 0 1 0 0 1 1 0 7 644.53125 625 MHz × 33/32 0 1 ½ 0 1 1 0 8 657.421875 657.421875 MHz 0 1 1 1 0 0 1 9 660.184152 657.421875 MHz × 239/238 ½ 0 0 1 0 0 0 10 669.3266 622.08 MHz × 255/238 ½ 0 ½ 1 0 1 1 11 672.1627 622.08 MHz × 255/236 ½ 0 1 1 0 1 0 12 690.569 622.08 MHz × 255/236 ½ ½ 0 1 1 0 1 13 693.48299 644.53125 MHz × 255/238 ½ ½ ½ 1 1 0 0 14 693.482991 644.53125 MHz × 255/237 ½ ½ 1 1 1 1 1 15 698.81236 622.08 × 255/237 ½ 1 0 1 1 1 0 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
