AD9558 datasheet(99/104 Pages) AD

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Data Sheet

AD9558

Rev. A | Page 99 of 104

Table 117. EEPROM Storage Sequence for Output PLL Settings

Address

Bits

Bit Name

Description

0x0E1D

[7:0]

APLL

The default value of this register is 0x08, which the controller interprets as a data instruction. Its

decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1), beginning at the

address that is specified by the next two bytes. The controller stores 0x08 in the EEPROM and

increments the EEPROM address pointer.

0x0E1E

[7:0]

0x0E1F

[7:0]

The default value of these two registers is 0x0400. Note that Register 0x0E1E and Register 0x0E1F

are the most significant and least significant bytes of the target address, respectively. Because the

previous register contains a data instruction, these two registers define a starting address (in this

case, 0x0400). The controller stores 0x0400 in the EEPROM and increments the EEPROM pointer by 2.

It then transfers nine bytes from the register map (beginning at Address 0x0400) to the EEPROM

and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The

nine bytes transferred correspond to APLL parameters in the register map.

Table 118. EEPROM Storage Sequence for Clock Distribution Settings

Address

Bits

Bit Name

Description

0x0E20

[7:0]

Clock distribution

The default value of this register is 0x15, which the controller interprets as a data instruction. Its

decimal value is 21, which tells the controller to transfer 22 bytes of data (21+1), beginning at the

address that is specified by the next two bytes. The controller stores 0x15 in the EEPROM and

increments the EEPROM address pointer.

0x0E21

[7:0]

0x0E22

[7:0]

The default value of these two registers is 0x0500. Note that Register 0x0E21 and Register 0x0E22

are the most significant and least significant bytes of the target address, respectively. Because the

previous register contains a data instruction, these two registers define a starting address (in this

case, 0x0500). The controller stores 0x0500 in the EEPROM and increments the EEPROM pointer by 2.

It then transfers 22 bytes from the register map (beginning at Address 0x0500) to the EEPROM and

increments the EEPROM address pointer by 23 (22 data bytes and one checksum byte). The

22 bytes transferred correspond to the clock distribution parameters in the register map.

0x0E23

[7:0]

I/O update

The default value of this register is 0x80, which the controller interprets as an I/O update

instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address

pointer.

Table 119. EEPROM Storage Sequence for Reference Input Settings

Address

Bits

Bit Name

Description

0x0E24

[7:0]

Reference inputs

The default value of this register is 0x03, which the controller interprets as a data instruction. Its

decimal value is 3, so this tells the controller to transfer four bytes of data (3 + 1), beginning at the

address that is specified by the next two bytes. The controller stores 0x03 in the EEPROM and

increments the EEPROM address pointer.

0x0E25

[7:0]

0x0E26

[7:0]

The default value of these two registers is 0x0600. Note that Register 0x0E25 and Register 0x0E26

are the most significant and least significant bytes of the target address, respectively. Because the

previous register contains a data instruction, these two registers define a starting address (in this

case, 0x0600). The controller stores 0x0600 in the EEPROM and increments the EEPROM pointer by 2.

It then transfers four bytes from the register map (beginning at Address 0x0600) to the EEPROM

and increments the EEPROM address pointer by 5 (four data bytes and one checksum byte). The

four bytes that are transferred correspond to the reference inputs parameters in the register map.

Table 120. EEPROM Storage Sequence for Frame Sync Settings

Address

Bit

Bit Name

Description

0x0E27

[7:0]

Frame sync

The default value of this register is 0x01, which the controller interprets as a data instruction. Its

decimal value is 1, which tells the controller to transfer two bytes of data (1 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x01 in the EEPROM and increments

the EEPROM address pointer.

0x0E28

[7:0]

0x0E29

[7:0]

The default value of these two registers is 0x0640. Note that Register 0x0E28 and Register 0x0E29

are the most significant and least significant bytes of the target address, respectively. Because the

previous register contains a data instruction, these two registers define a starting address (in this

case, 0x0640). The controller stores 0x0640 in the EEPROM and increments the EEPROM pointer by 2.

It then transfers two bytes from the register map (beginning at Address 0x0640) to the EEPROM

and increments the EEPROM address pointer by 3 (two data bytes and one checksum byte). The

two bytes transferred correspond to the reference inputs parameters in the register map.

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