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AD9558 Datasheet(PDF) 10 Page - Analog Devices |
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AD9558 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 104 page ![]() AD9558 Data Sheet Rev. A | Page 10 of 104 Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT TIMING SKEW 10 pF load Between OUT0 and OUT1 10 70 ps HSTL mode on both drivers; rising edge only; any divide value Between OUT0 and OUT3 105 222 ps HSTL mode on both drivers; rising edge only; any divide value Between OUT0 and OUT5 1.39 1.76 ns HSTL mode on both drivers; rising edge only; any divide value Between OUT1 and OUT2 (OUT1 and OUT2 Share the Same Divider) 1 12 ps HSTL mode on both drivers; rising edge only; any divide value Between OUT3 and OUT4 (OUT3 and OUT4 Share the Same Divider) 1 24 ps HSTL mode on both drivers; rising edge only; any divide value Across All OUT0 to OUT4 HSTL 105 235 ps HSTL mode on all drivers; rising edge only; any divide value Across All OUT0 to OUT4 LVDS 100 235 ps LVDS mode on all drivers; rising edge only; any divide value Additional Delay on One Driver by Changing Its Logic Type HSTL to LVDS −5 +1 +5 ps Positive value indicates that the LVDS edge is delayed relative to HSTL HSTL to 1.8 V CMOS −5 0 +5 ps Positive value indicates that the CMOS edge is delayed relative to HSTL HSTL to 3.3 V CMOS, Strong Mode The CMOS edge is delayed relative to HSTL OUT0 CMOS to OUT1 HSTL 3.53 3.59 ns OUT0 CMOS to OUT3 HSTL 3.55 3.65 ns OUT0 CMOS to OUT4 HSTL 3.56 3.68 ns OUT0 CMOS to OUT5 HSTL 4.84 5.1 ns 1 The listed values are for the slower edge (rise or fall). TIME DURATION OF DIGITAL FUNCTIONS Table 11. Parameter Min Typ Max Unit Test Conditions/Comments TIME DURATION OF DIGITAL FUNCTIONS EEPROM-to-Register Download Time 13 20 ms Using default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E3F) Register-to-EEPROM Upload Time 138 145 ms Using default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E3F ) Minimum Power-Down Exit Time 1 ms Time from power-down exit to system clock lock detect |
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