AD9558 datasheet(32/104 Pages) AD

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AD9558

Data Sheet

Rev. A | Page 32 of 104

TDC/PFD

The phase-frequency detector (PFD) is an all-digital block. It

compares the digital output from the TDC (which relates to the

active reference edge) with the digital word from the feedback

block. It uses a digital code pump and digital integrator (rather

than a conventional charge pump and capacitor) to generate the

error signal that steers the DCO frequency toward phase lock.

Programmable Digital Loop Filter

The AD9558 loop filter is a third order digital IIR filter that is

analogous to the third order analog loop shown in Figure 3

Figure 37. Third Order Analog Loop Filter

The AD9558 loop filter block features a simplified architecture

in which the user enters the desired loop characteristics directly

into the profile registers. This architecture makes the calculation

of individual coefficients unnecessary in most cases, while still

offering complete flexibility.

The AD9558 has two preset digital loop filters: high (88.5°) phase

margin and normal (70°) phase margin. The loop filter coefficients

are stored in Register 0x0317 to Register 0x0322 for high phase

margin and Register 0x0323 to Register 0x032E for normal phase

margin. The high phase margin loop filter is intended for

applications in which the closed-loop transfer function must

not have greater than 0.1 dB of peaking.

Bit 0 of the following registers selects which filter is used for

each profile: Register 0x070E for Profile A, Register 0x074E for

Profile B, Register 0x078E for Profile C, and Register 0x07CE

for Profile D.

The loop bandwidth for each profile is set in the following

registers: Register 0x070F to Register 0x0711 for Profile A,

to Register 0x0791 for Profile C, and Register 0x07CF to

The two preset conditions should cover all of the intended

applications for the AD9558. For special cases where these

conditions must be modified, the tools for calculating these

coefficients are available by contacting Analog Devices directly.

DPLL Digitally Controlled Oscillator Free Run Frequency

The AD9558 uses a Σ-Δ modulator (SDM) as a digitally controlled

oscillator (DCO). The DCO free run frequency can be calculated

from the following equation:

FTW0

SYS

freerun

dco

where FTW0 is the value in Register 0x0300 to Register 0x0303,

and fSYS is the system clock frequency. See the System Clock

section for information on calculating the system clock frequency.

Adaptive Clocking

The AD9558 can support adaptive clocking applications such as

asynchronous mapping and demapping. In these applications,

the output frequency can be dynamically adjusted by up to

±100 ppm from the nominal output frequency without manually

breaking the DPLL loop and reprogramming the part. This

function is supported for REFA only, not REFB.

The following registers are used in this function:

•

divider)

Writing to these registers requires an I/O update by writing

0x01 to Register 0x0005 before the new values take effect.

To make small adjustments to the output frequency, the user

can vary the FRAC1 and issue an I/O update. The advantage to

using only FRAC1 to adjust the output frequency is that the

DPLL does not briefly enter holdover. Therefore, the FRAC1 bit

can be updated as fast as the phase detector frequency of

the DPLL.

Writing to the N1 and MOD1 dividers allows for larger changes

to the output frequency. When the AD9558 detects that the N1

or MOD1 values have changed, it automatically enters and exits

holdover for a brief instant without any disturbance in the

output frequency. This limits how quickly the output frequency

can be adapted.

It is important to realize that the amount of frequency adjustment

is limited to ±100 ppm before the output PLL (APLL) needs a

recalibration. Variations that are larger than ±100 ppm are

possible, but the ability of the AD9558 to maintain lock over

temperature extremes may be compromised.

It is also important to remember that the rate of change in

output frequency depends on the DPLL loop bandwidth.

AD9558 Datasheet(PDF) 32 Page - Analog Devices

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