AD9558 datasheet(43/104 Pages) AD

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Data Sheet

AD9558

Rev. A | Page 43 of 104

WATCHDOG TIMER

The watchdog timer is a general purpose programmable timer.

To set the timeout period, the user writes to the 16-bit watchdog

timer register (Address 0x0210 to Address 0x0211). A value of

0b in this register disables the timer. A nonzero value sets the

timeout period in milliseconds (ms), giving the watchdog timer

a range of 1 ms to 65.535 sec. The relative accuracy of the timer

is approximately 0.1% with an uncertainty of 0.5 ms.

If enabled, the timer runs continuously and generates a timeout

event when the timeout period expires. The user has access to

the watchdog timer status via the IRQ mechanism and the

multifunction pins (M7 to M0). In the case of the multifunction

pins, the timeout event of the watchdog timer is a pulse that lasts

32 system clock periods.

There are two ways to reset the watchdog timer (thereby

preventing it from causing a timeout event). The first is by

writing a Logic 1 to the autoclearing clear watchdog bit in the

reset functions register (Register 0x0A03, Bit 0). Alternatively,

the user can program any of the multifunction pins to reset the

watchdog timer. This allows the user to reset the timer by means

of a hardware pin rather than by using a serial I/O port operation.

EEPROM

EEPROM Overview

The AD9558 contains an integrated 2048-byte, electrically

erasable, programmable read-only memory (EEPROM).

The AD9558 can be configured to perform a download at

power-up via the multifunction pins (M3 and M2), but uploads

and downloads can also be done on demand via the EEPROM

control registers (Address 0x0E00 to Address 0x0E03).

The EEPROM provides the ability to upload and download

configuration settings to and from the register map. Figure 44

shows a functional diagram of the EEPROM.

storage sequence area (referred to as the “scratch pad” in this

section) that enables the user to store a sequence of instructions

for transferring data to the EEPROM from the device settings

portion of the register map. Note that the default values for

these registers provide a sample sequence for saving/retrieving

all of the AD9558 EEPROM-accessible registers. Figure 44 shows

the connectivity between the EEPROM and the controller that

manages data transfer between the EEPROM and the register map.

The controller oversees the process of transferring EEPROM data

to and from the register map. There are two modes of operation

handled by the controller: saving data to the EEPROM (upload

mode) or retrieving data from the EEPROM (download mode).

In either case, the controller relies on a specific instruction set.

EEPROM

(0x000 TO 0x1FF)

DATA

EEPROM

ADDRESS

POINTER

DEVICE

SETTINGS

(0x0004 TO 0x0A0D)

SCRATCH PAD

(EEPROM STORAGE SEQUENCE)

(0x0E10 TO 0x0E45)

SERIAL

INPUT/OUTPUT

PORT

SCRATCH PAD

ADDRESS

POINTER

DEVICE

SETTINGS

ADDRESS

POINTER

EEPROM

CONTROLLER

Figure 44. EEPROM Functional Diagram

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