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XRT72L13 Datasheet(PDF) 162 Page - Exar Corporation

Part # XRT72L13
Description  M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
PDF  370 Pages
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT72L13 Datasheet(HTML) 162 Page - Exar Corporation

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XRT72L13
MULTIPLEXER/FRAMER IC
áç
áç
áç
áç
PRELIMINARY
REV. 1.0.6
150
NOTE: This bit-field is invalid if the XRT72L13 M13 device
is operating in the “ITU-T G.747” Mode.
Bit 2 - DS1 Channel # 6 Loop-back Status
This “Read-Only” bit-field indicates whether or not a
loop-back request has been detected for DS1 Chan-
nel # 6.
This bit-field will be set to “1” if a loop-back request
has been detected for DS1 Channel # 6. Conversely,
this bit-field will be set to “0” if a loop-back request
has NOT been detected for DS1 Channel # 6.
Bit 1 - DS1 Channel # 5 Loop-back Status
This “Read-Only” bit-field indicates whether or not a
loop-back request has been detected for DS1 Chan-
nel # 5.
This bit-field will be set to “1” if a loop-back request
has been detected for DS1 Channel # 5. Conversely,
this bit-field will be set to “0” if a loop-back request
has NOT been detected for DS1 Channel # 5.
Bit 0 - DS1 Channel # 4 Loop-back Status
This “Read-Only” bit-field indicates whether or not a
loop-back request has been detected for DS1 Chan-
nel # 4.
This bit-field will be set to “1” if a loop-back request
has been detected for DS1 Channel # 4. Conversely,
this bit-field will be set to “0” if a loop-back request
has NOT been detected for DS1 Channel # 4.
2.3.2.103 M12 DS2 # 3 Loopback Interrupt/Inter-
rupt Enable Register
Bit 7 - DS1 Channel 11 Loop-back Request Inter-
rupt Status
This “Reset-upon-Read” bit-field indicates whether
the “DS1 Channel 11 Loop-back Request” interrupt
has occurred or not.
This bit-field will be set to “1” if the “DS1 Channel 11
Loop-back Request Interrupt” has occurred since the
last read of this register.
This bit-field will be set to “0” if the “DS1 Channel 11
Loop-back Request” interrupt has NOT occurred
since the last read of this register.
NOTE: This bit-field is ignored if the XRT72L13 is config-
ured to operate in the “ITU-T G.747 Mode”.
Bit 6 - DS1 Channel 10 Loop-back Request Inter-
rupt Status
This “Reset-upon-Read” bit-field indicates whether
the “DS1 Channel 10 Loop-back Request” interrupt
has occurred or not.
This bit-field will be set to “1” if the “DS1 Channel 10
Loop-back Request Interrupt” has occurred since the
last read of this register.
This bit-field will be set to “0” if the “DS1 Channel 10
Loop-back Request” interrupt has NOT occurred
since the last read of this register.
Bit 5 - DS1 Channel 9 Loop-back Request Inter-
rupt Status
This “Reset-upon-Read” bit-field indicates whether
the “DS1 Channel 9 Loop-back Request” interrupt
has occurred or not.
This bit-field will be set to “1” if the “DS1 Channel 9
Loop-back Request Interrupt” has occurred since the
last read of this register.
This bit-field will be set to “0” if the “DS1 Channel 9
Loop-back Request” interrupt has NOT occurred
since the last read of this register.
Bit 4 - DS1 Channel 8 Loop-back Request Inter-
rupt Status
This “Reset-upon-Read” bit-field indicates whether
the “DS1 Channel 8 Loop-back Request” interrupt
has occurred or not.
This bit-field will be set to “1” if the “DS1 Channel 8
Loop-back Request Interrupt” has occurred since the
last read of this register.
This bit-field will be set to “0” if the “DS1 Channel 8
Loop-back Request” interrupt has NOT occurred
since the last read of this register.
Bit 3 - DS1 Channel 11 Loop-back Request Inter-
rupt Enable
M12 DS2 # 3 LOOP-BACK INTERRUPT/INTERRUPT ENABLE REGISTER (ADDRESS = 0X97)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
DS1
Channel 11
Loop-back
Request
Interrupt
Status
DS1
Channel 10
Loop-back
Request
Interrupt
Status
DS1
Channel 9
Loop-back
Request
Interrupt
Status
DS1
Channel 8
Loop-back
Request
Interrupt
Status
DS1
Channel 11
Loop-backj
Request
Interrupt
Enable
DS1
Channel 10
Loop-backj
Request
Interrupt
Enable
DS1
Channel 9
Loop-backj
Request
Interrupt
Enable
DS1
Channel 8
Loop-backj
Request
Interrupt
Enable
RUR
RUR
RUR
RUR
R/W
R/W
R/W/
R/W
00
000
000



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