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Signal Definitions (Continued)

2.2.2

PCI Interface Signals

Signal Name

BGA

Pin No.

SPGA

Pin No

Type

Description

FRAME#

(PU)

C13

(PU)

s/t/s

Frame

FRAME# is driven by the current master to indicate the beginning

and duration of an access. FRAME# is asserted to indicate a bus

transaction is beginning. While FRAME# is asserted, data trans-

fers continue. When FRAME# is deasserted, the transaction is in

the final data phase.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

IRDY#

(PU)

D14

(PU)

s/t/s

Initiator Ready

IRDY# is asserted to indicate that the bus master is able to com-

plete the current data phase of the transaction. IRDY# is used in

conjunction with TRDY#. A data phase is completed on any

SYSCLK in which both IRDY# and TRDY# are sampled asserted.

During a write, IRDY# indicates valid data is present on AD[31:0].

During a read, it indicates the master is prepared to accept data.

Wait cycles are inserted until both IRDY# and TRDY# are

asserted together.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

TRDY#

(PU)

B14

(PU)

s/t/s

Target Ready

TRDY#is assertedtoindicatethat thetarget agentis abletocom-

plete the current data phase of the transaction. TRDY# is used in

conjunction with IRDY#. A data phase is complete on any

SYSCLK in which both TRDY# and IRDY# are sampled asserted.

During a read, TRDY# indicates that valid data is present on

AD[31:0]. During a write, it indicates the target is prepared to

accept data. Wait cycles are inserted until both IRDY# and

TRDY# are asserted together.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

STOP#

C11

(PU)

A15

(PU)

s/t/s

Target Stop

STOP# is asserted to indicate that the current target is requesting

the master to stop the current transaction. This signal is used with

DEVSEL# to indicate retry, disconnect or target abort. If STOP# is

sampled active while a master, FRAME# will be deasserted and

the cycle will be stopped within three SYSCLKs. STOP# can be

asserted in the following cases:

A PCI master tries to access memory that has been locked by

another master. This condition is detected if FRAME# and LOCK#

are asserted during an address phase.

The PCI write buffers are full or a previously buffered cycle has

not completed.

Read cycles that cross cache line boundaries. This is conditional

based upon the programming of bit 1 in the PCI Control Function

2register.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

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