GX1 datasheet(49/247 Pages) NSC

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Processor Programming (Continued)

CR2 Register

Control Register 2 (R/W)

31:0

PFLA

Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the

address that caused the page fault.

CR1 Register

Control Register 1 (R/W)

31:0

RSVD

Reserved

CR0 Register

Control Register 0 (R/W)

Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing the state

of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change take effect.

Cache Disable: If CD = 1, no further cache line fills occur. However, data already present in the cache continues to

be used if the requested address hits in the cache. Writes continue to update the cache and cache invalidations

due to inquiry cycles occur normally. The cache must also be invalidated with a WBINVD instruction to completely

disable any cache activity.

Not Write-Through: If NW = 1, the on-chip cache operates in write-back mode. In write-back mode, writes are

issued to the external bus only for a cache miss, a line replacement of a modified line, execution of a locked instruc-

tion, or a line eviction as the result of a flush cycle. If NW = 0, the on-chip cache operates in write-through mode. In

write-through mode, all writes (including cache hits) are issued to the external bus. This bit cannot be changed if

LOCK_NW = 1 in CCR2.

28:19

RSVD

Reserved

Alignment Check Mask: If AM = 1, the AC bit in the EFLAGS register is unmasked and allowed to enable align-

ment check faults. Setting AM = 0 prevents AC faults from occurring.

RSVD

Reserved

Write Protect: Protects read-only pages from supervisor write access. WP = 0 allows a read-only page to be writ-

ten from privilege level 0-2. WP = 1 forces a fault on a write to a read-only page from any privilege level.

15:6

RSVD

Reserved

5NE

Numerics Exception: NE = 1 to allow FPU exceptions to be handled by interrupt 16. NE = 0 if FPU exceptions are

to be handled by external interrupts.

4RSVD

Reserved: Do not attempt to modify, always 1.

3TS

Task Switched: Set whenever a task switch operation is performed. Execution of a floating point instruction with

TS = 1 causes a DNA fault. If MP = 1 and TS = 1, a WAIT instruction also causes a DNA fault.

2EM

Emulate Processor Extension: If EM = 1, all floating point instructions cause a DNA fault 7.

1MP

Monitor Processor Extension: If MP = 1 and TS = 1, a WAIT instruction causes Device Not Available (DNA) fault

7. The TS bit is set to 1 on task switches by the CPU. Floating point instructions are not affected by the state of the

MP bit. The MP bit should be set to one during normal operations.

0PE

Protected Mode Enable: Enables the segment based protection mechanism. If PE = 1, protected mode is

enabled. If PE = 0, the CPU operates in real mode and addresses are formed as in an 8086-style CPU. Refer to

Section 3.9 “Protection” on page 91.

Table 3-7. CR4-CR0 Bit Definitions (Continued)

Bit

Name

Description

Table 3-8. Effects of Various Combinations of EM, TS, and MP Bits

CR0[3:1]

Instruction Type

WAIT

ESC

Execute

Fault 7

Execute

Fault 7

Execute

Fault 7

Execute

Fault 7

GX1 Datasheet(PDF) 49 Page - National Semiconductor (TI)

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