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Processor Programming (Continued)

3.3.1.4

EFLAGS Register

The EFLAGS register contains status information and con-

trols certain operations on the GX1 processor. The lower

16 bits of this register, referred to as the EFLAGS register,

is used when executing 8086 or 80286 code. Table 3-4

gives the bit formats for the EFLAGS register.

Table 3-4. EFLAGS Register

Bit

Name

Flag Type

Description

31:22

RSVD

Reserved: Set to 0.

System

Identification Bit: The ability to set and clear this bit indicates that the CPUID instruction is

supported. The ID can be modified only if the CPUID bit in CCR4 (Index E8h[7]) is set.

20:19

RSVD

Reserved: Set to 0.

System

Alignment Check Enable: In conjunction with the AM flag (bit 18) in CR0, the AC flag deter-

mines whether or not misaligned accesses to memory cause a fault. If AC is set, alignment

faults are enabled.

System

Virtual 8086 Mode: If set while in protected mode, the processor switches to virtual 8086 oper-

ation handling segment loads as the 8086 does, but generating exception 13 faults on privi-

leged opcodes. The VM bit can be set by the IRET instruction (if current privilege level is 0) or

by task switches at any privilege level.

Debug

Resume Flag: Used in conjunction with debug register breakpoints. RF is checked at instruc-

tion boundaries before breakpoint exception processing. If set, any debug fault is ignored on

the next instruction.

RSVD

Reserved: Set to 0.

System

Nested Task: While executing in protected mode, NT indicates that the execution of the cur-

rent task is nested within another task.

13:12

IOPL

System

I/O Privilege Level: While executing in protected mode, IOPL indicates the maximum current

privilege level (CPL) permitted to execute I/O instructions without generating an exception 13

fault or consulting the I/O permission bit map. IOPL also indicates the maximum CPL allowing

alteration of the IF bit when new values are popped into the EFLAGS register.

Arithmetic

Overflow Flag: Set if the operation resulted in a carry or borrow into the sign bit of the result

but did not result in a carry or borrow out of the high-order bit. Also set if the operation resulted

in a carry or borrow out of the high-order bit but did not result in a carry or borrow into the sign

bitofthe result.

Control

Direction Flag: When cleared, DF causes string instructions to auto-increment (default) the

appropriate index registers (ESI and/or EDI). Setting DF causes auto-decrement of the index

registers to occur.

System

Interrupt Enable Flag: When set, maskable interrupts (INTR input pin) are acknowledged and

serviced by the CPU.

Debug

Trap Enable Flag: Once set, a single-step interrupt occurs after the next instruction completes

execution. TF is cleared by the single-step interrupt.

7SF

Arithmetic

Sign Flag: Set equal to high-order bit of result (0 indicates positive, 1 indicates negative).

6ZF

Arithmetic

Zero Flag: Set if result is zero; cleared otherwise.

5RSVD

Reserved: Set to 0.

4AF

Arithmetic

Auxiliary Carry Flag: Set when a carry out of (addition) or borrow into (subtraction) bit position

3 of the result occurs; cleared otherwise.

3RSVD

Reserved: Set to 0.

2PF

Arithmetic

Parity Flag: Set when the low-order 8 bits of the result contain an even number of ones; other-

wise PF is cleared.

1RSVD

Reserved: Set to 1.

0CF

Arithmetic

Carry Flag: Set when a carry out of (addition) or borrow into (subtraction) the most significant

bit of the result occurs; cleared otherwise.

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