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Processor Programming (Continued)

3.3.2.1

Control Registers

A map of the Control Registers (CR0, CR1, CR2, CR3,

and CR4) is shown in Table 3-6 and the bit definitions are

given in Table 3-7. (These registers should not be confused

with the CRRn registers.) CR0 contains system control bits

which configure operating modes and indicate the general

state of the CPU. The lower 16 bits of CR0 are referred to

as the Machine Status Word (MSW).

When operating in real mode, any program can read and

write the control registers. In protected mode, however,

only privilege level 0 (most-privileged) programs can read

andwrite theseregisters.

L1 Cache Controller

The GX1 processor contains an on-board 16 KB unified

data/instruction write-back L1 cache. With the memory

controller on-board, the L1 cache requires no external

logic to maintain coherency. All DMA cycles automatically

snoop the L1 cache.

The CD bit (Cache Disable, bit 30) in CR0 globally con-

trols the operating mode of the L1 cache. LCD and LWT,

Local Cache Disable and Local Write-through bits in the

Translation Lookaside Buffer, control the mode on a page-

by-page basis. Additionally, memory configuration control

can specify certain memory regions as non-cacheable.

If the cache is disabled, no further cache line fills occur.

However, data already present in the cache continues to

be used. For the cache to be completely disabled, the

cache must be invalidated with a WBINVD instruction

after the cache has been disabled.

Write-back caching improves performance by relieving

congestion on slower external buses. With four dirty bits,

the cache marks dirty locations on a double-word

(DWORD) basis. This further reduces the number of

DWORD write operations needed during a replacement or

flush operation.

The GX1 processor will cache SMM regions, reducing

system management overhead to allow for hardware

emulation such as VGA.

Table 3-6. Control Registers Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

8765

43210

CR4 Register

Control Register 4 (R/W)

RSVD

CR3 Register

Control Register 3 (R/W)

PDBR (Page Directory Base Register)

RSVD

CR2 Register

Control Register 2 (R/W)

PFLA (Page Fault Linear Address)

CR1 Register

Control Register 1 (R/W)

RSVD

CR0 Register

Control Register 0 (R/W)

RSVD

Machine Status Word (MSW)

Table 3-7. CR4-CR0 Bit Definitions

Bit

Name

Description

CR4 Register

Control Register 4 (R/W)

31:3

RSVD

Reserved: Set to 0 (always returns 0 when read).

2TSC

Time Stamp Counter Instruction:

If = 1 RDTSC instruction enabled for CPL = 0 only; reset state.

If = 0 RDTSC instruction enabled for all CPL states.

1:0

RSVD

Reserved: Set to 0 (always returns 0 when read).

CR3 Register

Control Register 3 (R/W)

31:12

PDBR

Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.

11:0

RSVD

Reserved: Set to 0.

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