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Processor Programming (Continued)

3.3

The accessible registers in the processor are grouped into

three sets:

The Application Register Set contains the registers

frequently used by application programmers. Table 3-2

on page 44 shows the General Purpose, Segment,

Instruction Pointer and EFLAGS registers.

The System Register Set contains the registers typi-

cally reserved for operating systems programmers:

Control, System Address, Debug, Configuration, and

Test registers.

The Model Specific Register (MSR) Set is used to

monitor the performance of the processor or a specific

component within the processor. The Model Specific

Stamp Counter.

Each of these register sets are discussed in detail in the

subsections that follow. Additional registers to support inte-

grated GX1 processor subsystems are described in Sec-

tion 4.1 “Integrated Functions Programming Interface” on

page 97.

3.3.1

Application Register Set

The Application Register Set consists of the registers most

often used by the applications programmer. These regis-

ters are generally accessible, although some bits in the

EFLAGS registers are protected.

The General Purpose Register contents are frequently

modified by instructions and typically contain arithmetic

and logical instruction operands.

In real mode, Segment Registers contain the base

address for each segment. In protected mode, the Seg-

ment registers contain segment selectors. The segment

selectors provide indexing for tables (located in memory)

that contain the base address for each segment, as well as

other memory addressing information.

The Instruction Pointer Register points to the next

instruction that the processor will execute. This register is

automatically incremented by the processor as execution

progresses.

The EFLAGS Register contains control bits used to reflect

the status of previously executed instructions. This register

also contains control bits that affect the operation of some

instructions.

3.3.1.1

General Purpose Registers

The General Purpose Registers are divided into four data

registers, two pointer registers, and two index registers as

shown in Table 3-2 on page 44.

The Data Registers are used by the applications program-

mer to manipulate data structures and to hold the results of

logical and arithmetic operations. Different portions of gen-

eral data registers can be addressed by using different

names.

An “E” prefix identifies the complete 32-bit register. An “X”

suffix without the “E” prefix identifies the lower 16 bits of the

The lower two bytes of a data register are addressed with

an “H” suffix (identifies the upper byte) or an “L” suffix (identi-

fies the lower byte). These _L and _H portions of the data

registers act as independent registers. For example, if the

AH register is written to by an instruction, the AL register

bits remain unchanged.

The Pointer and Index registers are listed below.

SI or ESI

Source Index

DI or EDI

Destination Index

SP or ESP

Stack Pointer

BP or EBP

Base Pointer

These registers can be addressed as 16- or 32-bit registers,

with the “E” prefix indicating 32 bits. The Pointer and Index

registers can be used as general purpose registers; how-

ever, some instructions use a fixed assignment of these

registers. For example, repeated string operations always

use ESI as the source pointer, EDI as the destination

pointer, and ECX as a counter. The instructions that use

fixed registers include multiply and divide, I/O access,

string operations, stack operations, loop, variable shift and

rotate, and translate instructions.

The GX1 processor implements a stack using the ESP reg-

ister. This stack is accessed during the PUSH and POP

instructions, procedure calls, procedure returns, interrupts,

exceptions, and interrupt/exception returns. The GX1 pro-

cessor automatically adjusts the value of the ESP during

operations that result from these instructions.

The EBP register may be used to refer to data passed on

the stack during procedure calls. Local data may also be

placed on the stack and accessed with BP. This register

provides a mechanism to access stack data in high-level

languages.

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