GX1 datasheet(52/247 Pages) NSC

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Revision 1.0

Processor Programming (Continued)

Table 3-11. Configuration Registers

Bit

Name

Description

Index C1h

CCR1 — Configuration Control Register 1 (R/W)

Default Value = 00h

7:3

RSVD

Reserved: Set to 0.

2SMAC

System Management Memory Access:

If = 1: SMINT instruction can be recognized.

If = 0: SMINT instruction has no affect.

SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write this bit.

1USE_SMI

Enable SMM Pins:

If = 1: SMI# input pin is enabled. SMINT instruction can be recognized.

If = 0: SMI# pin is ignored.

SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write this bit.

0RSVD

Reserved: Set to 0.

Note:

Bits 1 and 2 are cleared to zero at reset.

Index C2h

CCR2 — Configuration Control Register 2 (R/W)

Default Value = 00h

7USE_SUSP

Enable Suspend Pins:

If = 1: SUSP# input and SUSPA# output are enabled.

If = 0: SUSP# input is ignored.

6RSVD

Reserved: This is a test bit that must be set to 0.

5RSVD

Reserved: Set to 0.

4WT1

Write-Through Region 1:

If = 1: Forces all writes to the address region between 640 KB to 1 MB that hit in the on-chip cache to

be issued on the external bus.

SUSP_HLT

Suspend on HALT:

If = 1: CPU enters Suspend mode following execution of a HALT instruction.

2LOCK_NW

Lock NW Bit:

If = 1: Prohibits changing the state of the NW bit (CR0[29]) (refer to Table 3-7 on page 49).

Set to 1 after setting NW.

1:0

RSVD

Reserved: Set to 0.

Note:

All bits are cleared to zero at reset.

Index C3h

CCR3 — Configuration Control Register 3 (R/W)

Default Value = 00h

LSS_34

Load/Store Serialize 3 GB to 4 GB:

If = 1: Strong R/W ordering imposed in address range C0000000h to FFFFFFFFh:

LSS_23

Load/Store Serialize 2 GB to 3 GB:

If = 1: Strong R/W ordering imposed in address range 80000000h to BFFFFFFFh:

LSS_12

Load/Store Serialize 1 GB to 2 GB:

If = 1: Strong R/W ordering imposed in address range 40000000h to 7FFFFFFFh

MAPEN

Map Enable:

If = 1: All configuration registers are accessible. All accesses to I/O Port 22h are trapped.

If = 0: Only configuration registers Index C1h-C3h, CDh-CFh FEh, FFh (CCRn, SMAR, DIRn) are

accessible. Other configuration registers (including PCR, SMHRn, GCR, VGACTL, VGAM0) are not

accessible.

SUSP_SMM_EN

Enable Suspend in SMM Mode:

If 0 = SUSP# ignored in SMM mode.

If 1 = SUSP# recognized in SMM mode.

2RSVD

Reserved: Set to 0.

1NMI_EN

NMI Enable:

If = 1: NMI is enabled during SMM.

If = 0: NMI is not recognized during SMM.

SMI_LOCK (CCR3[0]) must = 0 or the CPU must be in SMI mode to write to this bit.

GX1 Datasheet(PDF) 52 Page - National Semiconductor (TI)

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