GX1 datasheet(12/247 Pages) NSC

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Architecture Overview (Continued)

1.6

INTEGRATED FUNCTIONS

The GX1 processor integrates the following functions tradi-

tionally implemented using external devices:

• High-performance 2D graphics accelerator

• Separate CRT and TFT control from the display

controller

• SDRAM memory controller

• PCI bridge

The processor has also been enhanced to support VSA

technology implementation.

The GX1 processor implements a Unified Memory Archi-

tecture (UMA). By using DCT (Display Compression Tech-

nology) architecture, the performance degradation inherent

in traditional UMA systems is eliminated.

1.6.1

Graphics Accelerator

The graphics accelerator is a full-featured GUI accelerator.

The graphics pipeline implements a bitBLT engine for

frame buffer bitBLTs and rectangular fills. Additional

instructions in the integer unit may be processed, as the

bitBLT engine assists the CPU in the bitBLT operations that

take place between system memory and the frame buffer.

This combination of hardware and software is used by the

display driver to provide very fast bidirectional transfers

between system memory and the frame buffer. The bitBLT

engine also draws randomly oriented vectors, and scan-

lines for polygon fill. All of the pipeline operations described

in the following list can be applied to any bitBLT operation.

• Pattern Memory: Render with 8x8 dither, 8x8 mono-

chrome, or 8x1 color pattern.

• Color Expansion: Expand monochrome bitmaps to full

depth 8- or 16-bit colors.

• Transparency: Suppresses drawing of background

pixels for transparent text.

• Raster Operations: Boolean operation combines

source, destination, and pattern bitmaps.

1.6.2

Display Controller

The display port is a direct interface to the Geode I/O com-

panion (i.e., CS5530) which drives a TFT flat panel display,

LCD panel, or a CRT display.

The display controller (video generator) retrieves image

data from the frame buffer, performs a color-look-up if

required, inserts the cursor overlay into the pixel stream,

generates display timing, and formats the pixel data for out-

put to a variety of display devices. The display controller

contains DCT architecture that allows the GX1 processor

to refresh the display from a compressed copy of the frame

buffer. DCT architecture typically decreases the screen

refresh bandwidth requirement by a factor of 15 to 20, min-

imizing bandwidth contention.

1.6.3

XpressRAM Memory Subsystem

The memory controller drives a 64-bit SDRAM port directly.

The SDRAM memory array contains both the main system

memory and the graphics frame buffer. Up to four module

banks of SDRAM are supported. Each module bank can

have two or four component banks depending on the mem-

ory size and organization. The maximum configuration is

four module banks with four component banks, each pro-

viding a total of 16 open banks. The maximum memory

size is 512 MB.

The memory controller handles multiple requests for mem-

ory data from the GX1 processor, the graphics accelerator

and the display controller. The memory controller contains

extensive buffering logic that helps minimize contention for

memory bandwidth between graphics and CPU requests.

The memory controller cooperates with the internal bus

controller to determine the cacheability of all memory refer-

ences.

1.6.4

PCI Controller

The GX1 processor incorporates a full-function PCI inter-

face module that includes the PCI arbiter. All accesses to

external I/O devices are sent over the PCI bus, although

most memory accesses are serviced by the SDRAM con-

troller. The internal bus interface unit contains address

mapping logic that determines if memory accesses are tar-

getedfor theSDRAMor for the PCI bus. ThePCI busina

GX1 based system is 3.3 volt only. Do not connect 5 volt

devices on this bus.

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