GX1 datasheet(35/247 Pages) NSC

35 / 247 page

Revision 1.0

www.national.com

Signal Definitions (Continued)

LOCK#

B11

(PU)

B16

(PU)

s/t/s

Lock Operation

LOCK# indicates an atomic operation that may require multiple

transactions to complete. When LOCK# is asserted, nonexclusive

transactions may proceed to an address that is not currently

locked (at least 16 bytes must be locked). A grant to start a trans-

action on PCI does not guarantee control of LOCK#. Control of

LOCK# is obtained under its own protocol in conjunction with

GNT#. It is possible for different agents to use PCI while a single

master retains ownership of LOCK#. The arbiter can implement a

complete system lock. In this mode, if LOCK# is active, no other

master can gain access to the system until the LOCK# is deas-

serted.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

DEVSEL#

(PU)

E15

(PU)

s/t/s

Device Select

DEVSEL# indicates that the driving device has decoded its

address as the target of the current access. As an input,

DEVSEL# indicates whether any device on the bus has been

selected. DEVSEL# will also be driven by any agent that has the

ability to accept cycles on a subtractive decode basis. As a mas-

ter, if no DEVSEL# is detected within and up to the subtractive

decode clock, a master abort cycle will result except for special

cycles which do not expect a DEVSEL# returned.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

PERR#

A11

(PU)

D16

(PU)

s/t/s

Parity Error

PERR# is used for the reporting of data parity errors during all PCI

transactions except a Special Cycle. The PERR# line is driven

two SYSCLKs after the data in which the error was detected,

which is one SYSCLK after the PAR that was attached to the

data. The minimum duration of PERR# is one SYSCLK for each

data phase in which a data parity error is detected. PERR# must

be driven high for one SYSCLK before going to TRI-STATE. A tar-

get asserts PERR# on write cycles if it has claimed the cycle with

DEVSEL#. The master asserts PERR# on read cycles.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

SERR#

C12

(PU)

A17

(PU)

System Error

SERR# may be asserted by any agent for reporting errors other

than PCI parity. The intent is to have the PCI central agent assert

NMI to the processor. When the Parity Enable bit is set in the

Memory Controller Configuration register, SERR# will be asserted

upon detecting a parity error on read operations from DRAM.

REQ[2:0]#

D3,

H3,

(PU)

E3,

K2,

(PU)

Request Lines

REQ# indicates to the arbiter that an agent desires use of the bus.

Each master has its own REQ# line. REQ# priorities are based on

the arbitration scheme chosen.

This pin is internally connected to a weak (>20-kohm) pull-up

resistor.

2.2.2

PCI Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No

Type

Description

GX1 Datasheet(PDF) 35 Page - National Semiconductor (TI)

GX1 Datasheet(HTML) 35 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL