GX1 datasheet(62/247 Pages) NSC

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Revision 1.0

Processor Programming (Continued)

3.3.3

Model Specific Register

The Model Specific Register (MSR) Set is used to monitor

the performance of the processor or a specific component

within the processor.

A MSR can be read using the RDMSR instruction, opcode

0F32h. During a MSR read, the contents of the particular

MSR, specified by the ECX register, is loaded into the

EDX:EAX registers.

AMSR canbewrittenusing theWRMSR instruction,

opcode 0F30h. During a MSR write, the contents of

EDX:EAX are loaded into the MSR specified in the ECX

The RDMSR and WRMSR instructions are privileged

instructions.

The GX1 processor contains one 64-bit Model Specific

3.3.4

Time Stamp Counter

The TSC, (MSR[10]), is a 64-bit counter that counts the

internal CPU clock cycles since the last reset. The TSC

uses a continuous CPU core clock and continues to count

clock cycles unless the processor is in Suspend.

The TSC is read using a RDMSR instruction, opcode

0F32h, with the ECX register set to 10h. During a TSC

read, the contents of the TSC is loaded into the EDX:EAX

registers.

The TSC is written to using a WRMSR instruction, opcode

0F30h with the ECX register set to 10h. During a TSC

write, the contents of EDX:EAX are loaded into the TSC.

The RDMSR and WRMSR instructions are privileged

instructions.

In addition, the TSC can be read using the RDTSC instruc-

tion, opcode 0F31h. The RDTSC instruction loads the con-

tents of the TSC into EDX:EAX. The use of the RDTSC

instruction is restricted by the TSC flag (bit 2) in the CR4

instruction can be executed at any privilege level. When the

TSC bit = 1, the RDTSC instruction can only be executed at

privilege level 0.

GX1 Datasheet(PDF) 62 Page - National Semiconductor (TI)