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GX1 Datasheet(PDF) 47 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 47 Page - National Semiconductor (TI) |
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47 / 247 page  Revision 1.0 47 www.national.com Processor Programming (Continued) 3.3.2 System Register Set The System Register Set, shown in Table 3-5, consists of registers not generally used by application programmers. These registers are typically employed by system level pro- grammers who generate operating systems and memory management programs. Associated with the System Reg- ister Set are certain tables and segments which are listed in Table 3-5. The Control Registers control certain aspects of the GX1 processor such as paging, coprocessor functions, and seg- ment protection. The Configuration Registers are used to define the GX1 CPU setup including cache management. The Debug Registers provide debugging facilities for the GX1 processor and enable the use of data access break- points and code execution breakpoints. The Test Registers provide a mechanism to test the con- tents of both the on-chip 16 KB cache and the Translation Lookaside Buffer (TLB). The Descriptor Table Register hold descriptors that man- age memory segments and tables, interrupts and task switching. The tables are defined by corresponding regis- ters. The two Task State Segment Tables defined by TSS reg- ister are used to save and load the computer state when switching tasks. The ID Registers allow BIOS and other software to identify the specific CPU and stepping. System Management Mode (SMM) control information is stored in the SMM Registers. Table 3-5 lists the system register sets along with their size and function. Table 3-5. System Register Set Group Name Function Width (Bits) Control Registers CR0 System Control Register 32 CR2 Page Fault Linear Address Register 32 CR3 Page Directory Base Register 32 CR4 Time Stamp Counter 32 Configuration Registers CCRn Configuration Con- trol Registers 8 Debug Registers DR0 Linear Breakpoint Address 0 32 DR1 Linear Breakpoint Address 1 32 DR2 Linear Breakpoint Address 2 32 DR3 Linear Breakpoint Address 3 32 DR6 Breakpoint Status 32 DR7 Breakpoint Control 32 Test Registers TR3 Cache Test 32 TR4 Cache Test 32 TR5 Cache Test 32 TR6 TLB Test Control 32 TR7 TLB Test Data 32 Descriptor Tables GDT General Descriptor Table 32 IDT Interrupt Descriptor Table 32 LDT Local Descriptor Table 16 Descriptor Table Registers GDTR GDT Register 32 IDTR IDT Register 32 LDTR LDT Register 16 Task State Segment and Registers TSS Task State Segment Table 16 TR TSS Register Setup 16 ID Registers DIRn Device Identification Registers 8 SMM Registers SMARn SMM Address Region Registers 8 SMHRn SMM Header Addresses 8 Performance Registers PCR0 Performance Con- trol Register 8 |
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