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GX1 Datasheet(PDF) 92 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # GX1
Description  Processor Series Low Power Integrated x86 Solution
PDF  247 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

GX1 Datasheet(HTML) 92 Page - National Semiconductor (TI)

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Revision 1.0
Processor Programming (Continued)
3.9.3
Privilege Level Transfers
Atask’s CPL can be changed only through intersegment
control transfers using gates or task switches to a code seg-
ment with a different privilege level. Control transfers result
from exception and interrupt servicing and from execution
of the CALL, JMP, INT, IRET and RET instructions.
There are five types of control transfers that are summa-
rized in Table 3-37. Control transfers can be made only
when the operation causing the control transfer references
the correct descriptor type. Any violation of these descriptor
usage rules causes a general protection fault.
Any control transfer that changes the CPL within a task
results in a change of stack. The initial values for the stack
segment (SS) and stack pointer (ESP) for privilege levels 0,
1, and 2 are stored in the TSS. During a JMP or CALL con-
trol transfer, the SS and ESP are loaded with the new stack
pointer and the previous stack pointer is saved on the new
stack. When returning to the original privilege level, the
RET or IRET instruction restores the SS and ESP of the
less-privileged stack.
3.9.3.1
Gates
Gate descriptors described in Section “Gate Descriptors”
on page 74, provide protection for privilege transfers among
executable segments. Gates are used to transition to rou-
tines of the same or a more privileged level. Call gates,
interrupt gates and trap gates are used for privilege transfers
within a task. Task gates are used to transfer between
tasks.
Gates conform to the standard rules of privilege. In other
words, gates can be accessed by a task if the effective priv-
ilege level (EPL) is the same or more privileged than the
gate descriptor’s privilege level (DPL).
Table 3-37. Descriptor Types Used for Control Transfer
Type of Control Transfer
Operation Types
Descriptor
Referenced
Descriptor
Table
Intersegment within the same privilege
level.
JMP, CALL, RET, IRET1
Code Segment
GDT or LDT
Intersegment to the same or a more
privileged level. Interrupt within task
(could change CPL level).
CALL
Gate Call
GDT or LDT
Interrupt Instruction, Exception,
External Interrupt
Trap or Interrupt Gate
IDT
Intersegment to a less privileged level
(changes task CPL).
RET, IRET1
Code Segment
GDT or LDT
Task Switch via TSS
CALL, JMP
Task State Segment
GDT
Task Switch via Task Gate
CALL, JMP
Task Gate
GDT or LDT
IRET2, Interrupt Instruction,
Exception, External Interrupt
Task Gate
IDT
1.
NT = 0 (Nested Task bit in EFLAGS, bit 14)
2.
NT =1 (Nested Task bit in EFLAGS, bit 14)



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