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GX1 Datasheet(PDF) 75 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 75 Page - National Semiconductor (TI) |
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75 / 247 page  Revision 1.0 75 www.national.com Processor Programming (Continued) Task State Segments Descriptors The CPU enables rapid task switching using JMP and CALL instructions that refer to Task State Segment (TSS) descriptors. During a switch, the complete task state of the current task is stored in its TSS, and the task state of the requested task is loaded from its TSS. The TSSs are defined through special segment descriptors and gates. The Task Register (TR) holds 16-bit descriptors that con- tain the base address and segment limit for each task state segment. The TR is loaded and stored via the LTR and STR instructions, respectively. The TR can be accessed only during protected mode and can be loaded when the privilege level is 0 (most privileged). When the TR is loaded, the TR selector field indexes a TSS descriptor that must reside in the Global Descriptor Table (GDT). Only the 16-bit selector of a TSS descriptor in the TR is accessible. The BASE, TSS LIMIT and ACCESS RIGHT fields are program invisible. During task switching, the processor saves the current CPU state in the TSS before starting a new task. The TSS can be either a 386/486-type 32-bit TSS (see Table 3-26) or a 286-type 16-bit TSS (see Table 3-27). Task Gate Descriptors. A task gate descriptor provides controlled access to the descriptor for a task switch. The DPLofthe task gateisusedtocontrol access. The selec- tor’s RPL and the CPL of the procedure must be a higher level (numerically less) than the DPL of the descriptor. The RPLinthe task gate is not used. TheI/O MapBaseAddress fieldinthe 32-bit TSSpoints to an I/O permission bit map that often follows the TSS at location +68h. Table 3-26. 32-Bit Task State Segment (TSS) Table1 31 16 15 0 I/O Map Base Address 00000000000 0000 T +64h 0000000000 000000 Selector for Task’s LDT +60h 0000000000 000000 GS +5Ch 0000000000 000000 FS +58h 0000000000 000000 DS +54h 0000000000 000000 SS +50h 0000000000 000000 CS +4Ch 0000000000 000000 ES +48h EDI +44h ESI +40h EBP +3Ch ESP +38h EBX +34h EDX +30h ECX +2Ch EAX +28h EFLAGS +24h EIP +20h CR3 +1Ch 0000000000 000000 SS for CPL = 2 +18h ESP for CPL = 2 +14h 0000000000 000000 SS for CPL = 1 +10h ESP for CPL = 1 +Ch 0000000000 000000 SS for CPL = 0 +8h ESP for CPL = 0 +4h 0000000000 000000 Back Link (Old TSS Selector) +0h 1. 0 = Reserved |
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