GX1 datasheet(89/247 Pages) NSC

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Processor Programming (Continued)

When SMI nesting is disabled, the processor holds off

external SMI interrupts until the currently executing SMM

code exits. When SMI nesting is enabled, the processor

can proceed with the SMI. The SMM service routine will

guarantee that no internal SMIs are generated in SMM, so

the processor ignores such events. If the internal and exter-

nal SMI signals are received simultaneously, then the inter-

nal SMI is given priority to avoid losing the event.

The state diagram of the SMI_NEST and Nested SMI Sta-

tusbitsare showninFigure3-11witheachstate explained

next.

When the processor is outside of SMM, Nested SMI

Status is always clear and SMI_NEST is set high.

The first-level SMI interrupt is received by the

processor. The microcode clears SMI_NEST, sets

Nested SMI Status high and saves the previous value

of Nested SMI Status (0) in the SMM header.

The first-level SMM service routine saves the header

and sets SMI_NEST high to re-enable SMI interrupts

from SMM.

A second-level (nested) SMI interrupt is received by

theprocessor. ThisSMI is takeneventhough the

processor is in SMM because the SMI_NEST bit is set

high. The microcode clears SMI_NEST, sets Nested

SMI Status high and saves the previous value of

Nested SMI Status (1) in the SMM header.

The second-level SMM service routine saves the

header and sets SMI_NEST to re-enable SMI inter-

rupts within SMM. Another level of nesting could occur

during this period.

The

second-level

SMM

service

routine

clears

SMI_NEST to disable SMI interrupts, then restores its

SMM header.

The second-level SMM service routine executes an

RSM. The microcode sets SMI_NEST, and restores

the Nested SMI Status (1) based on the SMM header.

The first-level SMM service routine clears SMI_NEST

to disable SMI interrupts, then restores its SMM

header.

The first-level SMM service routine executes an RSM.

The microcode sets SMI_NEST high and restores the

Nested SMI Status (0) based on the SMM header.

When the processor is outside of SMM, Nested SMI Status

is always clear and SMI_NEST is set high.

Figure 3-11. SMI Nesting State Machine

SMI_NEST

Nested SMI Status

GX1 Datasheet(PDF) 89 Page - National Semiconductor (TI)

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