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Processor Programming (Continued)

3.6

INTERRUPTS AND EXCEPTIONS

The processing of either an interrupt or an exception

changes the normal sequential flow of a program by trans-

ferring program control to a selected service routine.

Except for SMM interrupts, the location of the selected ser-

vice routine is determined by one of the interrupt vectors

stored in the interrupt descriptor table.

True interrupts are hardware interrupts and are generated

by signal sources external to the CPU. All exceptions (includ-

ing so-called software interrupts) are produced internally by

the CPU.

3.6.1

Interrupts

External events can interrupt normal program execution by

using one of the three interrupt pins on the GX1 processor:

• Non-maskable Interrupt (No pin, see note)

• Maskable Interrupt (INTR pin)

• SMM Interrupt (SMI# pin)

Note:

There is not an NMI pin on the GX1 processor.

Generation of an NMI interrupt is not possible.

However, software can generate an NMI by setting

bit 2 of CCR7. (See the CCR7 register on

page 53.)

For most interrupts, program transfer to the interrupt rou-

tine occurs after the current instruction has been com-

pleted. When the execution returns to the original program,

it begins immediately following the interrupted instruction.

The NMI interrupt cannot be masked by software and

always uses interrupt vector two to locate its service rou-

tine. Since the interrupt vector is fixed and is supplied inter-

nally, no interrupt acknowledge bus cycles are performed.

This interrupt is normally reserved for unusual situations

such as parity errors and has priority over INTR interrupts.

Once NMI processing has started, no additional NMIs are

processed until an IRET instruction is executed, typically at

the end of the NMI service routine. If the NMI is re-asserted

before execution of the IRET instruction, one and only one

NMI rising edge is stored and then processed after execu-

tion of the next IRET.

During the NMI service routine, maskable interrupts may

be enabled. If an unmasked INTR occurs during the NMI

service routine, the INTR is serviced and execution returns

to the NMI service routine following the next IRET. If a

HALT instruction is executed within the NMI service routine,

the CPU restarts execution only in response to RESET, an

unmasked INTR or a System Management Mode (SMM)

interrupt. NMI does not restart CPU execution under this

condition.

The INTR interrupt is unmasked when the Interrupt

Enable Flag (IF, bit 9) in the EFLAGS register is set to 1

(See the EFLAGS register in Table 3-4 on page 46). Except

for string operations, INTR interrupts are acknowledged

between instructions. Long string operations have interrupt

windows between memory moves that allow INTR inter-

rupts to be acknowledged.

When an INTR interrupt occurs, the CPU performs an inter-

rupt-acknowledge bus cycle. During this cycle, the CPU

reads an 8-bit vector that is supplied by an external inter-

rupt controller. This vector selects which of the 256 possi-

ble interrupt handlers will be executed in response to the

interrupt.

The SMM interrupt has higher priority than either INTR or

NMI. After SMI# is asserted, program execution is passed

to an SMM service routine that runs in SMM address space

reserved for this purpose. The remainder of this section

does not apply to the SMM interrupts. SMM interrupts are

described in greater detail later in Section 3.7 “System

Management Mode” on page 83.

3.6.2

Exceptions

Exceptions are generated by an interrupt instruction or a

program error. Exceptions are classified as traps, faults or

aborts depending on the mechanism used to report them

and the restartability of the instruction which first caused

the exception.

A Trap exception is reported immediately following the

instruction that generated the trap exception. Trap excep-

tions are generated by execution of a software interrupt

instruction (INTO, INT3, INTn, BOUND), by a single-step

operation or by a data breakpoint.

Software interrupts can be used to simulate hardware inter-

rupts. For example, an INTn instruction causes the proces-

sor to execute the interrupt service routine pointed to by the

nth vector in the interrupt table. Execution of the interrupt

service routine occurs regardless of the state of the IF flag

(bit 9) in the EFLAGS register.

The one byte INT3, or breakpoint interrupt (vector 3), is a

particular case of the INTn instruction. By inserting this one

byte instruction in a program, the user can set breakpoints

in the code that can be used during debug.

Single-step operation is enabled by setting the TF bit (bit 8)

in the EFLAGS register. When the TF is set, the CPU gen-

erates a debug exception (vector 1) after the execution of

every instruction. Data breakpoints also generate a debug

exception and are specified by loading the debug registers

(DR0-DR3, see Table 3-12 on page 55) with the appropri-

ate values.

A Fault exception is reported before completion of the

instruction that generated the exception. By reporting the

fault before instruction completion, the CPU is left in a state

that allows the instruction to be restarted and the effects of

the faulting instruction to be nullified. Fault exceptions

include divide-by-zero errors, invalid opcodes, page faults

and coprocessor errors. Debug exceptions (vector 1) are

also handled as faults (except for data breakpoints and sin-

gle-step operations). After execution of the fault service

routine, the instruction pointer points to the instruction that

caused the fault.

An Abort exception is atypeoffault exceptionthatis

severe enough that the CPU cannot restart the program at

the faulting instruction. The double fault (vector 8) is the

only abort exception that occurs on the CPU.

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