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Processor Programming (Continued)

3.6.4

Interrupt and Exception Priorities

As the CPU executes instructions, it follows a consistent

policy for prioritizing exceptions and hardware interrupts.

The priorities for competing interrupts and exceptions are

listed in Table 3-30. SMM interrupts always take prece-

dence. Debug traps for the previous instruction and next

instructions are handled as the next priority. When NMI and

maskable INTR interrupts are both detected at the same

instruction boundary, the GX1 processor services the NMI

interrupt first.

The CPU checks for exceptions in parallel with instruction

decoding and execution. Several exceptions can result

from a single instruction. However, only one exception is

generated upon each attempt to execute the instruction.

Each exception service routine should make the appropri-

ate corrections to the instruction and then restart the

instruction. In this way, exceptions can be serviced until the

instruction executes properly.

The CPU supports instruction restart after all faults, except

when an instruction causes a task switch to a task whose

Task State Segment (TSS) is partially not present. A TSS

can be partially not present if the TSS is not page aligned

and one of the pages where the TSS resides is not cur-

rently in memory.

Table 3-30. Interrupt and Exception Priorities

Priority

Description

Notes

Reset.

Caused by the assertion of RESET.

SMM hardware interrupt.

SMM interrupts are caused by SMI# asserted and always have high-

est priority.

Debug traps and faults from previous instruction.

Includes single-step trap and data breakpoints specified in the debug

registers.

Debug traps for next instruction.

Includes instruction execution breakpoints specified in the debug reg-

isters.

Non-maskable hardware interrupt.

Caused by NMI asserted.

Maskable hardware interrupt.

Caused by INTR asserted and IF = 1.

Faults resulting from fetching the next instruction.

Includes segment not present, general protection fault and page fault.

Faults resulting from instruction decoding.

Includes illegal opcode, instruction too long, or privilege violation.

WAIT instruction and TS = 1 and MP = 1.

Device not available exception generated.

ESC instruction and EM = 1 or TS = 1.

Device not available exception generated.

Floating point error exception.

Caused by unmasked floating point exception with NE = 1.

Segmentation faults (for each memory reference

required by the instruction) that prevent transferring

the entire memory operand.

Includes segment not present, stack fault, and general protection

fault.

Page Faults that prevent transferring the entire

memory operand.

Alignment check fault.

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