GX1 datasheet(37/247 Pages) NSC

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Signal Definitions (Continued)

DQM[7:0]

Refer

Table 2-3

Refer

Table 2-5

Data Mask Control Bits

During memory read cycles, these outputs control whether the

SDRAM output buffers are driven on the MD bus or not. All DQM

signals are asserted during read cycles.

During memory write cycles, these outputs control whether or not

MD data will be written into the SDRAM.

DQM[0] is associated with MD[7:0].

DQM[7] is associated with MD[63:56].

SDCLK[3:0]

AE4,

AF5,

AE5,

AF4

AM8,

AK10,

AL7,

AK8

SDRAM Clocks

The SDRAM devices sample all the control, address, and data

based on these clocks.

SDCLK_IN

AE8

AK12

SDRAM Clock Input

The GX1 processor samples the memory read data on this clock.

Works in conjunction with the SDCLK_OUT signal.

SDCLK_OUT

AF8

AL13

SDRAM Clock Output

This output is routed back to SDCLK_IN. The board designer

should vary the length of the board trace to control skew between

SDCLK_IN and SDCLK.

2.2.3

Memory Controller Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

2.2.4

Video Interface Signals

Signal Name

BGA

Pin No

SPGA

Pin No

Type

Description

PCLK

AC1

AJ1

Pixel Port Clock

PCLK is the pixel dot clock output. It clocks the pixel data from

the GX1 processor to the CS5530.

VID_CLK

Video Clock

VID_CLK is the video port clock to the CS5530.

DCLK

AB1

AD4

Dot Clock

The DCLK input is driven from the CS5530 and is the pixel dot

clock. In some cases this clock can be a 2x multiple of PCLK

CRT_HSYNC

AD2

CRT Horizontal Sync

CRT Horizontal Sync establishes the line rate and horizontal

retrace interval for an attached CRT. The polarity is programma-

ble. See DC-Timing_CFG register in Table 4-29 on Page 145 for

programming information.

CRT_VSYNC

AA3

AH2

CRT Vertical Sync

CRT Vertical Sync establishes the screen refresh rate and verti-

cal retrace interval for an attached CRT. The polarity is program-

mable. See DC-Timing_CFG register in Table 4-29 on Page 145

for programming information.

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