GX1 datasheet(60/247 Pages) NSC

60 / 247 page

www.national.com

Revision 1.0

Processor Programming (Continued)

Table 3-17. TR5-TR3 Bit Definitions

Bit

Name

Description

TR5 Register (R/W)

11:4

Line Selection

Line Selection:

Physical address bits [11:4] used to select one of 256 lines.

3:2

Set/DWord

Selection

Set/DWORD Selection:

Cache read: Selects which of the four sets in the cache is used as the source for data

transferred to the cache flush buffer.

Cache write: Selects which of the four sets in the cache is used as the destination for data transferred from

the cache fill buffer.

Flush buffer read: Selects which of the four DWORDs in the flush buffer is used during a TR3 read.

Fill buffer write: Selects which of the four DWORDs in the fill buffer is written during a TR3 write.

1:0

Control Bits

Control Bits:

00 = Flush read or fill buffer write.

01 = Cache write.

10 = Cache read.

11 = Cache flush.

TR4 Register (R/W)

31:12

Upper Tag

Address

Upper Tag Address:

Cache read: Upper 20 bits of tag address of the selected entry.

Cache write: Data written into the upper 20 bits of the tag address of the selected entry.

Valid Bit

Valid Bit:

Cache read: Valid bit for the selected entry.

Cache write: Data written into the valid bit for the selected entry.

9:7

LRU Bits

LRU Bits:

Cache read: The LRU bits for the selected line when scratchpad is disabled.

xx1 = Set 0 or Set 1 most recently accessed.

xx0 = Set 2 or Set 3 most recently accessed.

x1x = Most recent access to Set 0 or Set 1 was to Set 0.

x0x = Most recent access to Set 0 or Set 1 was to Set 1.

1xx = Most recent access to Set 2 or Set 3 was to Set 2.

0xx = Most recent access to Set 2 or Set 3 was to Set 3.

Cache write: Ignored.

6:3

Dirty Bits

Dirty Bits:

Cache read: The dirty bits for the selected entry (one bit per DWORD).

Cache write: Data written into the dirty bits for the selected entry.

2:0

RSVD

Reserved: Set to 0.

TR3 Register (R/W)

31:0

Cache Data

Cache Data:

Flush buffer read: Data accessed from the cache flush buffer.

Fill buffer write: Data to be written into the cache fill buffer.

GX1 Datasheet(PDF) 60 Page - National Semiconductor (TI)

GX1 Datasheet(HTML) 60 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL