FDC37M607 datasheet(117/182 Pages) SMSC

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Table 50 - Status Register

C/D

IBF

OBF

Status Register

This register is cleared on a reset. This register

is read-only for the Host and read/write by the

FDC37M60x CPU.

UD Writable by FDC37M60x CPU. These bits

are user-definable.

C/D (Command

Data)

This

bit

specifies

whether the input data register contains data or

a command (0 = data, 1 = command). During a

host data/command write operation, this bit is

set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.

IBF (Input Buffer Full) - This flag is set to “1”

whenever the host system writes data into the

input data register.

Setting this flag activates

the FDC37M60x CPU's nIBF (MIRQ) interrupt if

enabled. When the FDC37M60x CPU reads the

input

data

(DBB),

this

bit

automatically

reset

and

the

interrupt

cleared. There is no output pin associated with

this internal signal.

OBF

(Output Buffer Full) - This flag is set to

whenever the FDC37M60x CPU write to the

output data register (DBB).

When the host

system reads the output data register, this bit is

automatically reset.

EXTERNAL CLOCK SIGNAL

The FDC37M60x Keyboard Controller clock

source is a 12 MHz clock generated from a

14.318 MHz clock. The reset pulse must last for

at least 24 16 MHz clock periods. The pulse-

width requirement applies to both internally (Vcc

POR) and externally generated reset signals. In

powerdown mode, the external clock signal is

not loaded by the chip.

DEFAULT RESET CONDITIONS

The FDC37M60x has one source of reset: an

external reset via the RESET_DRV pin. Refer to

Table 51 for the effect of each type of reset on

the internal registers.

Table 51 - Resets

DESCRIPTION

HARDWARE RESET (RESET)

KCLK

Weak High

KDAT

Weak High

MCLK

Weak High

MDAT

Weak High

Host I/F Data Reg

N/A

Host I/F Status Reg

00H

N/A: Not Applicable

FDC37M607 Datasheet(PDF) 117 Page - SMSC Corporation

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