FDC37M607 datasheet(119/182 Pages) SMSC

119 / 182 page

119

Bit 0 of Port 92, which generates the nALT_RST

signal, is used to reset the CPU under program

control.

This

signal

AND’ed

together

externally with the reset signal (nKBDRST) from

the keyboard controller to provide a software

means of resetting the CPU.

This provides a

faster means of reset than is provided by the

keyboard controller. Writing a 1 to bit 0 in the

Port 92 Register causes this signal to pulse low

for a minimum of 6µs, after a delay of a

minimum of 14µs. Before another nALT_RST

pulse can be generated, bit 0 must be set to 0

either by a system reset of a write to Port 92.

Upon reset, this signal is driven inactive high (bit

0 in the Port 92 Register is set to 0).

If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is

set to 1, then a pulse is generated by writing a 1

to bit 0 of the Port 92 Register and this pulse is

AND’ed with the pulse generated from the 8042.

This pulse is output on pin KRESET and its

polarity is controlled by the GPI/O polarity

configuration.

8042

P92

Pulse

Gen

KBDRST

KRST_GA20

Bit 2

Bit 0

P20

KRST

nALT_RST

6us

14us

6us

14us

Note: When Port 92 is disabled,

writes are ignored and reads

return undefined values.

KRESET Generation

FDC37M607 Datasheet(PDF) 119 Page - SMSC Corporation

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