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BT8376EPF Datasheet(PDF) 36 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 36 Page - Synaptics Incorporated. |
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36 / 323 page  2.0 Circuit Description Bt8370/8375/8376 2.2 Receive Line Interface Unit Fully Integrated T1/E1 Framer and Line Interface 2-8 Conexant N8370DSE 2.2.2 Clock Recovery 2.2.2.1 Phase Locked Loop The Receive Phase Locked Loop (RPLL) recovers the line rate clock from the Data Slicer dual rail outputs. The RPLL generates a recovered clock that tracks the jitter in the data from the Data Slicer, and sustains the data-to-clock phase relationship in the absence of incoming pulses. Figure 2-7 illustrates the Receive LIU’s input clock and data jitter tolerance. Figure 2-7. Receive Input Jitter Tolerance 0.1 1 10 100 1000 10000 0.1 1 10 100 1000 10000 100000 Sine Wave Jitter Frequency (Hz) [Log Scale] Data Jitter Tolerance Clock Jitter Tolerance TR 62411 (T1) Min. Tolerance G. 824 (T1) Min. Tolerance Reg. G. 823 (E1) Min. Tolerance 138 UI 28 UI 1.5 UI 5 UI 0.35 UI .22 UI 0.2UI 0.1UI |
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