BT8376EPF datasheet(82/323 Pages) CONEXANT

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2.0 Circuit Description

Bt8370/8375/8376

2.8 Transmitter

Fully Integrated T1/E1 Framer and Line Interface

2-54

Conexant

N8370DSE

2.8.1 External Transmit Data Link

The External Data Link (DL3) allows the system to supply externally any bits in

any time slot of all frames, odd frames, or even frames, including T1 framing bits.

Pin access to the DL3 transmitter is provided through TDLCKO and TDLI, which

serve as the TDL3 clock output (TDLCKO) and data input (TDLI). The mode of

the pins is selected using TDL_IO bit in the Programmable Input/Output register

[PIO; addr 018].

Control of DL3 format is provided in two registers: External Data Link Time

Slot [DL3_TS; addr 015] and External Data Link Bit [DL3_BIT; addr 016].

Transmit DL3 is set up by selecting the bit(s) [DL3_BIT], and time slot [TS[4:0];

addr 015] to be overwritten, and then enabling the data link [DL3EN; addr 015].

Enabling the data link starts TDLCKO for gating the NRZ data provided on

TDLI. See Figure 2-29.

2.8.2 Transmit Data Links

The XMTR contains two independent data link controllers (DL1, DL2):

a Performance Report Message (PRM) generator and a Bit-Oriented Protocol

(BOP) transceiver. DL1 and DL2 can be programmed to send and receive HDLC

formatted messages in the Message Oriented Protocol (MOP) mode, or

unformatted serial data can be sent and received in any combination of bits within

a selected time slot or F-bit channel. The PRM message generator can

automatically send 1-second performance reports. The BOP transceiver can

preemptively transmit BOP messages, such as ESF Yellow Alarm.

2.8.2.1 Data Link

Controllers

The Bt8370 and Bt8375 provide two internal data link controllers, and the Bt8376

provides a single controller. DL1 and DL2 control the serial data channels, which

operate in multiples of 4 kbps to the maximum 64 kbps time slot rate. This is done

by selecting a combination of bits from either odd, even, or all frames. Both data

link controllers support ESF Facilities Data Link (FDL), SLC-96 data link,

Sa data link, Common Channel Signaling (CCS), Signaling System #7 (SS7);

ISDN LAPD channels; Digital Multiplexed Interface (DMI) signaling in TS24;

and the latest ETSI V.51 and V.52 signaling channels. DL1 and DL2 each contain

a 64-byte transmit buffer which function either as programmable length circular

buffers in transparent (unformatted) mode, or as full-length data FIFOs in

formatted (HDLC) mode.

Figure 2-29. Transmit External Data Link Waveforms

NOTE(S):

This example shows bits 1, 2, 7, and 8 of TS9 selected. Any combination of time slot bits can be selected.

TDLI

TDLCKO

TS8

TS9

TS10

BT8376EPF Datasheet(PDF) 82 Page - Synaptics Incorporated.

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