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BT8376EPF Datasheet(PDF) 62 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 62 Page - Synaptics Incorporated. |
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62 / 323 page ![]() 2.0 Circuit Description Bt8370/8375/8376 2.5 Receive System Bus Fully Integrated T1/E1 Framer and Line Interface 2-34 Conexant N8370DSE The RSB maps line rate time slots to system bus time slots. The 24- (DS1) or 32- (CEPT) line rate time slots can be mapped to 24, 32, 64, or 128 system bus time slots as listed in Table 2-5. The system bus rate must be greater than or equal to the line rate, except for 1.536 MHz bus mode. The RSB, illustrated in Figure 2-18, consists of a timebase, slip buffer, signaling buffer, and signaling stack. Table 2-5. RSB Interface Time Slot Mapping Line Rate (MHz) Source Channels System Bus Rate (MHz) Destination Time Slots 1.544 24 1.536 24 24 1.544 24 24 2.048 32 24 4.096 64 24 8.192 128 2.048 32 2.048 32 32 4.096 64 32 8.192 128 Figure 2-18. RSB Diagram TSBCKI RSIG STACK RSIG Buffer RSIG Local RSLIP Buffer RPHASE RNRZ AIS From Receiver RSB Timebase + + RSIGO RPCMO SIGFRZ RINDO RFSYNC RMSYNC RSBCKI CLADI CLADO Remote Channel Loopback Local Channel Loopback |
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