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BT8376EPF Datasheet(PDF) 37 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 37 Page - Synaptics Incorporated. |
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37 / 323 page ![]() Bt8370/8375/8376 2.0 Circuit Description Fully Integrated T1/E1 Framer and Line Interface 2.3 Jitter Attenuator N8370DSE Conexant 2-9 2.3 Jitter Attenuator The Jitter Attenuator (JAT), illustrated in Figure 2-8, attenuates jitter in the receive or transmit path, but not both simultaneously. In the receive configuration, the line signal is recovered by the RLIU and is dejittered before it is decoded by the RCVR. In the transmit configuration, the encoded signal from the transmit block is dejittered before it is transmitted by the Transmit Line Interface Unit (TLIU). The JAT receive/transmit configuration is done through the JDIR bit in the Jitter Attenuator Configuration register [JAT_CR; addr 002]. The JAT can also be completely disabled using the Jitter Attenuation (JEN) bit in the JAT_CR register. Figure 2-8. Jitter Attenuator Block Diagram Tin Tout Rin Rout or RJAT TJAT To/From TLIU JCLK RXCLK To RLIU From RLIU TXCLK JCLK To JPHASE Depth (to CLAD) (from CMUX) |
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