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BT8376EPF Datasheet(PDF) 71 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 71 Page - Synaptics Incorporated. |
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71 / 323 page ![]() Bt8370/8375/8376 2.0 Circuit Description Fully Integrated T1/E1 Framer and Line Interface 2.6 Clock Rate Adapter N8370DSE Conexant 2-43 Tables 2-8 and 2-9 list examples of program values for selecting various CLADO and CLADI frequencies. Typically, only 1 selection is needed for a given system configuration. The processor reconfigures the timing reference [CEN; addr 090] as needed to respond to system conditions where the primary reference is unavailable. 2.6.1 Configuring the CLAD Registers Step 1 Choose a CLADO output frequency. Table 2-8 lists all possible CLADO output clock frequencies. For system bus applications, valid CLADO frequencies are 1544 kHz, 1536 kHz, 2048 kHz, 4096 kHz, and 8192 kHz. Step 2 Configure OSEL and XSEL from Table 2-8. OSEL and XSEL together select the CLADO output frequency. In some cases, there are two options for generating the desired output signal. Selecting an option with both T1/E1 and XSEL settings equal to don’t-care (X in the table) allows greater flexibility in subsequent options below, and also results in a fixed CLADO frequency when switching framer operation between T1 and E1 modes. Step 3 If CLADI is the timing reference source (CEN = 1), select the desired CLAD timing reference frequency from Table 2-9. If CEN = 0, the CLAD reference is RXCLK (line rate), TXCLK (line rate), or free run (REFCKI) and Table 2-9 is not applicable. Table 2-8. CLADO Frequencies Selection CLADO (kHz) T1/E1 OSEL XSEL 1024 X 0 X 2048 X 1 X 07 0 4096 X 2 X 07 1 8192 X 3 X 07 2 2560 X 4 X 1536 X 6 X 1544 1 7 0 X5 X 3088 1 7 1 6176 1 7 2 12352 1 7 3 16384 0 7 3 X8 X NOTE(S): X = Don’t care |
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