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BT8376EPF Datasheet(PDF) 1 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 1 Page - Synaptics Incorporated. |
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1 / 323 page  Data Sheet N8370DSE June 30, 1999 Bt8370/8375/8376 Fully Integrated T1/E1 Framer and Line Interface The Bt8370/8375/8376 is a family of single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces, operating at 1.544 Mbps or 2.048 Mbps. These devices combine a sophisticated framer, transmit and receive slip buffers, and an on-chip physical line interface to provide a complete T1/E1 transceiver. The fully featured Bt8370 and short-haul Bt8375 and Bt8376 devices provide a programmable clock rate adapter for simplifying system bus interfacing. The adapter synthesizes standard clock signals from the receive or transmit line rate clocks or from an external reference. Operations are controlled through memory-mapped registers accessible via a parallel microprocessor port. Current ANSI, ETSI, ITU-T, and Bellcore standards are supported for alarm and error monitoring, signaling supervision (e.g., LAPD/SS7), per-channel trunk conditioning, and Facility Data Link (FDL) maintenance. A serial Time Division Multiplexed (TDM) system bus interface allows the backplane Pulse Code Modulation (PCM) data highway to operate at rates from 1.536 to 8.192 Mbps. Extensive test and diagnostic functions include a full set of digital and analog loopbacks, PRBS test pattern generation, BER meter, and forced error insertion. The physical line interface circuit recovers clock and data from analog signals with +3 to –43 dB cable attenuation, appropriate for both short (–18 dB) and long-haul T1/E1 applications. Receive line equalization (EQ) and transmit Line Build Out (LBO) filters are implemented using Digital Signal Processor (DSP) circuits for reliable performance. Data and/or clock jitter attenuation can be inserted on either the receive or transmit path. The transmit section includes precision pulse shaping and amplitude pre-emphasis for cross connect applications, as well as a set of LBO filters for long-haul Channel Service Unit (CSU) applications. A complementary driver output is provided to couple 75/100/120 Ω lines via an external transformer. Functional Block Diagram Receive System Bus Transmit System Bus CLAD I/O Dual-Rail/NRZ/ External DL3 Motorola/Intel Processor Bus Test Port Receive Analog Transmit Analog T1/E1 Transmit Framer TX Slip Buffer RX Slip Buffer T1/E1 Receive Framer Overhead Insertion Clock Rate Adaptor Control/Status Registers JTAG Data Link Controllers DL1 + DL2 EQ RPLL Pulse LBO TPLL TX or RX Jitter Attenuator ZCS Decode ZCS Encode RX TX Distinguishing Features • Single-chip T1/E1 framer with short/long-haul physical line interface • Frames to popular T1/E1 standards: – T1: SF, ESF, SLC 96, T1DM – E1: PCM -30, G.704, G.706, G.732 ISDN primary rate • On-chip physical line interface compatible with: – DSX-1/E1 short-haul signals – DS-1 (T1.403) and ETSI long-haul signals • Two-frame transmit and receive PCM slip buffers • Clock rate adapter synthesizes jitter attenuated system clocks from an internal or external reference • Parallel 8-bit microprocessor port supports Intel or Motorola buses • Automated Facility Data Link (FDL) management • BERT generation and counting • Two full-duplex HDLC controllers for data link and LAPD/SS7 signaling • B8ZS/HDB3/Bit 7 zero suppression • 80-pin MQFP surface-mount package • Operates from a single +5 Vdc ±5% power supply • Low-power CMOS technology Applications • T1/E1 Channel Service Unit/Data Service Unit (CSU/DSU) • Digital Access Cross-Connect Systems (DACS) • T1/E1 Multiplexer (MUX) • PBXs and PCM channel bank • T1/E1 HDSL terminal unit • ISDN Primary Rate Access (PRA) |
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