BT8376EPF datasheet(21/323 Pages) CONEXANT

21 / 323 page

Bt8370/8375/8376

1.0 Pin Descriptions

Fully Integrated T1/E1 Framer and Line Interface

1.1 Pin Assignments

N8370DSE

Conexant

1-5

Microprocessor Interface (MPU) (Continued)

ONESEC

1-second Timer

PIO

Controls or marks 1-second interval used for status reporting. When

input, the timer is aligned to ONESEC rising edge. When output, rising

edge indicates start of each 1-second interval. Typically, 1 device in a

multi-line system is configured to output ONESEC to synchronize other

Bt8370/8375/8376 status reports on a common 1-second interval.

INTR*

Interrupt Request

Open drain active-low output signifies 1 or more pending interrupt

requests. INTR* goes to high-impedance state after processor has

serviced all pending interrupt requests.

DTACK*

Data Transfer

Acknowledge

Open drain active-low output signifies in-progress data transfer cycle.

DTACK* remains asserted (low) for as long as AS* and CS* are both

active-low. DTACK* is only implemented during synchronous Motorola

processor interface modes. Refer to the timing diagrams in Section 5.5,

MPU Interface Timing.

Line Interface Unit (LIU)

XOE

Transmit Output

Enable

Active-high input enables XTIP and XRING output drivers; otherwise, both

outputs are placed in high-impedance state. XOE contains internal pullup

so systems that do not require three-stated outputs can leave XOE

unconnected. XOE needs to be disabled during Power-On Reset (POR) and

re-enabled after configuring the part. Refer to Power-On Reset procedure

in Section 2.10.4,

Device Reset.

RTIP, RRING

Receive Tip/Ring

Differential AMI data inputs for direct connection to receive transformer.

VSET

Voltage Reference Set

I/O

Constant voltage output. Must be connected to an external 1% resistor

equal to 14 k

Ω to ground (GND[4] pin 62). The VSET resistor sets the

internal precision current reference of 100

µA and also controls the

transmit pulse height.

XTIP, XRING

Transmit Tip/Ring

Complementary AMI data outputs for direct connection to transmit

transformer. Optionally, both outputs are three-stated when XOE is

negated.

Digital Transmitter (XMTR)

TCKI

Tx Clock Input

Primary TX line rate clock applied on TCKI, or the system chooses from 1

of four different clocks to act as TX clock source (see [CMUX; addr 01A]).

The selected source is used to clock digital transmitter signals TPOSI,

TNEGI, TPOSO, TNEGO, TNRZO, MSYNCO, TDLI, and TDLCKO. If TSLIP is

bypassed, selected source also clocks TSB signals.

ACKI

All Ones Clock

System optionally applies ACKI for AIS transmission, if the selected

primary transmit clock source fails. ACKI is either manually or

automatically switched to replace TCKI (see [AISCLK; addr 068]). Systems

without an AIS clock must tie ACKI to ground.

Table 1-1. Hardware Signal Definitions (2 of 8)

Pin Label

Signal Name

I/O

Definition

BT8376EPF Datasheet(PDF) 21 Page - Synaptics Incorporated.

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