BT8376EPF datasheet(20/323 Pages) CONEXANT

20 / 323 page

1.0 Pin Descriptions

Bt8370/8375/8376

1.1 Pin Assignments

Fully Integrated T1/E1 Framer and Line Interface

1-4

Conexant

N8370DSE

Table 1-1. Hardware Signal Definitions (1 of 8)

Pin Label

Signal Name

I/O

Definition

Microprocessor Interface (MPU)

RST*

Hardware Reset

RST* low-to-high transition forces registers to their default, power-up

state and forces all PIO pins to the input state. RST* is not mandatory,

because internal power on reset circuit performs an identical function.

RST* can be applied asynchronously, but must remain asserted for a

minimum of 2 clock cycles (external MCLK or internal 32 MHz) for the

low-to-high transition to be sampled and detected (see also [RESET; addr

001]).

MCLK

Processor Clock

System applies MCLK in the range of 8–36 MHz for external clock

(CLKMD = 1) and synchronous bus modes (SYNCMD = 1). During internal

clock modes (CLKMD = 0), the Bt8370/8375/8376 uses an internally

generated 32 MHz clock to control processor timing, and MCLK input is

ignored.

MOTO*

Motorola Bus mode

Selects Intel- or Motorola-style microprocessor interface. DS*, R/W*,

A[8:0], and AD[7:0] functions are affected.

0 = Motorola; AD[7:0] is data, A[8:0] is address, DS* is data strobe,

and R/W* indicates the read (high) or write (low) data direction.

1 = Intel; AD[7:0] is multiplexed address/data, A[7:0] ignored, A[8] is

address line, DS* is read strobe (RD*), and R/W* is write strobe (WR*).

SYNCMD

Sync mode

Selects whether read/write cycle timing is synchronous with MCLK.

Supports Intel- or Motorola-style buses:

0 = Asynchronous bus; read data enable and write data input latch are

asynchronously controlled by CS*, DS*, and R/W* signals. Latched write

data is still synchronized internally to 32 MHz clock for transfer to

addressed register.

1 = Synchronous bus; applicable only if the external clock is also

selected (CLKMD = 1). MCLK rising edge samples CS*, DS*, and R/W* to

determine valid read/write cycle timing. Allows 0 wait state processor

cycles for MCLK speeds up to 36 MHz, for M68000 type buses.

CLKMD

Clock mode

Selects whether MCLK is enabled (high) or ignored (low). When enabled,

MCLK frequency determines update rate of internal registers and sampling

rate of CS*, DS*, and R/W* signals.

A[8:0]

Address Bus

AS* falling edge asynchronously latches A[8:0] (Motorola) or A[8] (Intel)

to identify 1 register for subsequent read/write data transfer cycle.

AD[7:0]

Data Bus or Address

Data

I/O

Multiplexed address/data (Intel) or only data (Motorola). Refer to MOTO*

signal definition.

AS* (ALE)

Address Strobe

For all processor bus modes, AS* falling edge asynchronously latches

address from A[8:0] (Motorola) or from A[8] and AD[7:0] (Intel). For sync

modes (SYNCMD = 1), each read/write data cycle requires both AS* and

CS* active-low on MCLK rising edge.

CS*

Chip Select

Active-low enables read/write decoder. Active-high ends current read or

write cycle and places data bus output in high impedance.

DS*(RD*)

Data Strobe or

Read Strobe

Active-low read data strobe (RD*) for MOTO* = 1, or read/write data

strobe (DS*) for MOTO* = 0.

R/W*(WR*)

Read/Write Direction

or Write Strobe

Active-low write data strobe (WR*) for MOTO* = 1, or read/write data

select (R/W*) for MOTO = 0.

BT8376EPF Datasheet(PDF) 20 Page - Synaptics Incorporated.

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