BT8376EPF datasheet(63/323 Pages) CONEXANT

63 / 323 page

Bt8370/8375/8376

2.0 Circuit Description

Fully Integrated T1/E1 Framer and Line Interface

2.5 Receive System Bus

N8370DSE

Conexant

2-35

2.5.1 Timebase

The RSB timebase synchronizes RFSYNC, RMSYNC, and RINDO with the

Receive System Bus Clock (RSBCKI). The RSBCKI can be slaved to 4 clock

sources: Receive System Bus Clock Input (RSBCKI), Transmit System Bus

Clock Input (TSBCKI), Clock Rate Adapter Input (CLADI), or Clock Rate

Adapter Output (CLADO). The RSB clock selection is made through the Clock

Input Mux register [CMUX; addr 01A]. The system bus clock can also be

configured to run at twice the data rate by setting the X2CLK bit in the System

Bus Interface Configuration register [SBI_CR; addr 0D0].

RFSYNC and RMSYNC can be individually configured as inputs or outputs

[PIO; addr 018]. RFSYNC and RMSYNC must be configured as inputs when the

RSB timebase is slaved to the system bus [SBI_OE; addr 0D0]. RFSYNC and

RMSYNC must be configured as outputs when the RSB timebase is master of the

system bus. RFSYNC and RMSYNC can also be configured as rising or falling

edge outputs [RSB_CR; addr 0D1]. In addition to having RFSYNC and

RMSYNC active on the frame boundary, a programmable offset is available to

select the time slot and bit offset in the frame. See the Receive System Bus Sync

Time Slot Offset [RSYNC_TS; addr 0D3] and the Receive System Bus Sync Bit

Offset [RSYNC_BIT; addr 0D2].

BT8376EPF Datasheet(PDF) 63 Page - Synaptics Incorporated.