BT8376EPF datasheet(44/323 Pages) CONEXANT

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2.0 Circuit Description

Bt8370/8375/8376

2.4 Receiver

Fully Integrated T1/E1 Framer and Line Interface

2-16

Conexant

N8370DSE

2.4.3 Error Counters

The following Performance Monitoring (PM) counters are available in the

RCVR: Framing Bit Errors (FERR), CRC Errors (CERR), Line Code Violations

(LCV), and Far End Block Errors (FEBE). All PM count registers are reset on

read unless LATCH_CNT is set in the Alarm/Error/Counter Latch Configuration

counts coincident with the 1-second timer interrupt [ISR6; addr 005]. One-second

latching of PM counts is required if AUTO_PRM responses are enabled. All PM

counters can be disabled during RLOF, RLOS, and RAIS, using the STOP_CNT

bit in the LATCH register.

NOTE:

If STOP_CNT is negated, error monitoring during RLOF conditions will

detect FERR, CERR, and FEBE according to the last known frame

alignment.

2.4.3.1 Frame Bit Error

Counter

The 12-bit Framing Bit Error Counter [FERR; addr 050 and 051] increments each

time a receive Ft, Fs, T1DM, FPS, or FAS error is detected. Fs (T1) and NFAS

(E1) errors can be included in the FERR count by setting FS_NFAS in Receive

Alarm Signal Configuration [RALM; addr 045]. An interrupt is available to

indicate that the FERR counter overflowed in the Counter Overflow Interrupt

Status register [ISR4; addr 007].

2.4.3.2 CRC Error

Counter

The 10-bit Cyclic Redundancy Check Error Counter [CERR; addr 052 and 053]

increments each time a receive CRC4 (E1) or CRC6 (T1) error is detected. An

interrupt is available to indicate that the CERR counter overflowed in ISR4.

2.4.3.3 LCV Error

Counter

The 16-bit Line Code Violation Error Counter [LCV; addr 054 and 055]

increments each time a receive Bipolar Violation (BPV)—not including line

coding—is detected. The LCV count can include EXZ if EXZ_LCV in the

Receive Alarm Signal Configuration register [RALM; addr 045] is set. EXZ can

be configured [RZCS; addr 040] to be 8 or 16 successive 0s, following a 1. An

interrupt is available to indicate that the LCV counter overflowed in ISR4.

2.4.3.4 FEBE Counter

The 10-bit Far End Block Error (FEBE) counter [FEBE; addr 056 and 057]

increments each time the RCVR encounters an E1 far-end block error. An

interrupt is available to indicate that the FEBE counter overflowed in ISR4.

BT8376EPF Datasheet(PDF) 44 Page - Synaptics Incorporated.

BT8376EPF Datasheet(HTML) 44 Page - Synaptics Incorporated.

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