BT8376EPF datasheet(24/323 Pages) CONEXANT

24 / 323 page

1.0 Pin Descriptions

Bt8370/8375/8376

1.1 Pin Assignments

Fully Integrated T1/E1 Framer and Line Interface

1-8

Conexant

N8370DSE

Transmit System Bus (TSB)

TSBCKI

TSB Clock Input

Bit clock and I/O signal timing for TSB according to system bus mode (see

[SBI_CR; addr 0D0]). System chooses from 1 of four different clocks to

act as TSB clock source (see [CMUX; addr 01A]). Rising or falling edge

clocks are independently configurable for data signals TPCMI, TSIGI,

TINDO and sync signals TFSYNC and TMSYNC (see [TPCM_NEG and

TSYN_NEG; addr 0D4]). When configured to operate at twice the data rate,

TSB clock is internally divided by two before clocking TSB data signals.

TPCMI

TSB Data Input

Serial data formatted into TSB frames consisting of DS0 channel time

slots and optional F-bits. One group of 24 T1 time slots or 32 E1 time slots

is selected from up to four available groups; data from the group is

sampled by TSBCKI, then sent towards transmitter output. Time slots are

routed through transmit slip buffer (see [TSLIPn; addr 140–17F])

according to TSLIP mode (see [TSBI; addr 0D4]). F-bits are taken from the

start of each TSB frame or from within an embedded time slot (see

[EMBED; addr 0D0]) and optionally inserted into the transmitter output

(see [TFRM; addr 072] register).

TSIGI

TSB Signaling Input

Serial data formatted into TSB frames containing ABCD signaling bits for

each system bus time slot. Four bits of TSIGI time slot carry signaling

state for each accompanying TPCMI time slot. Signaling state of every

time slot is sampled during first frame of the TSB multiframe, and then

transferred into transmit signaling buffer [TSIGn; addr 120–13F].

TINDO

TSB Time Slot

Indicator

Active-high output pulse marks selective transmit system bus time slots

as programmed by SBCn [addr 0E0–0FF]. TINDO occurs on TSBCKI rising

or falling edges as selected by TPCM_NEG (see [TSBI; addr 0D4]).

TFSYNC

TSB Frame Sync

PIO

Input or output TSB frame sync (see [TFSYNC_IO; addr 018]). TFSYNC

output is active-high for 1 TSB clock cycle at programmed offset bit

location (see [TSYNC_BIT; addr 0D5]), marking offset bit position within

each TSB frame and repeating once every 125

µs. When transmit framer is

also enabled, TSB timebase and TFSYNC output frame alignment are

established by transmit framer's examination of TPCMI serial data input.

When TFSYNC is programmed as an input, the low-to-high signal

transition is detected and aligns TSB timebase to programmed offset bit

value. TSB timebase flywheels at 125

µs frame interval after the last

TFSYNC is applied.

TMSYNC

TSB Multiframe Sync

PIO

Input or output TSB multiframe sync (see [TMSYNC_IO; addr 018]).

TMSYNC output is active-high for 1 TSB clock cycle at programmed offset

bit location (see [TSYNC_BIT; addr 0D5]), marking offset bit position

within each TSB multiframe and repeating once every 6 ms coincident

with TFSYNC. When transmit framer is also enabled, TSB timebase and

TMSYNC output multiframe alignment are established by transmit

framer's examination of TPCMI serial data input. When TMSYNC is

programmed as an input, the low-to-high signal transition is detected and

aligns TSB timebase to the programmed offset bit value and first frame of

the multiframe. TSB timebase flywheels at 6 ms multiframe interval after

the last TMSYNC is applied. If system bus applies TMSYNC input, TFSYNC

input is not needed.

Table 1-1. Hardware Signal Definitions (5 of 8)

Pin Label

Signal Name

I/O

Definition

BT8376EPF Datasheet(PDF) 24 Page - Synaptics Incorporated.

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