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BT8376EPF Datasheet(PDF) 19 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 19 Page - Synaptics Incorporated. |
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19 / 323 page ![]() Bt8370/8375/8376 1.0 Pin Descriptions Fully Integrated T1/E1 Framer and Line Interface 1.1 Pin Assignments N8370DSE Conexant 1-3 Figure 1-2. Bt8370/8375/8376 Logic Diagram NOTE(S): (1) Refer to Figure 1-1 Bt8370/8375/8376 Pinout Diagram. (2) Pins 27 and 39 shown twice for clarity; pin function controlled by PIO (addr 018). (3) Pin 66 is not connected for the Bt8376 device. 28 29 78 1 26 (1) (1) 5 2 4 6 79 73 74 61 65 51 41 38 76 70 71 37 34 33 45 Hardware Reset Processor Clock Motorola Bus mode Sync Bus mode Clock mode Address Bus Data Bus or Address/Data Address Strobe Chip Select Read or Data Strobe Write Strobe or Read/Write Transmit Output Enable Receive Tip Receive Ring Voltage Reference Set Tx Clock In All Ones Clock Tx Positive In/TDL Data In Tx Negative In/TDL Clock Rx Clock In Rx Positive In Rx Negative In TSB Clock TSB Data TSB Signaling RSB Clock RST* MCLK MOTO* SYNCMD CLKMD A[8:0] AD[7:0] AS* (ALE) CS* DS* (RD*) R/W*(WR*) XOE RTIP RRING VSET TCKI ACKI TPOSI/TDLI TNEGI/TDLCKO RCKI RPOSI RNEGI TSBCKI TPCMI TSIGI RSBCKI ONESEC INTR* DTACK* XTIP XRING TCKO TPOSO/TNRZO TNEGO/MSYNCO RCKO RPOSO/RDLO RNEGO/RDLCKO TINDO TFSYNC TMSYNC RPCMO RSIGO RINDO RFSYNC RMSYNC SIGFRZ CLADO TDO 32 3 77 58 57 64 27 39 48 47 46 27 35 36 42 40 39 43 44 80 66 54 Microprocessor Receive, Transmit PIO O O O O O O O O O O O PIO PIO O O O PIO PIO O O O I I I I I I I/O I I I I I I I I/O I I I PIO I I I I I I I 1-second Timer Interrupt Request Data Transfer Acknowledge Transmit Tip Transmit Ring Tx Negative Out/(2) Rx Clock Out Rx Positive Out/RDL Data Out Rx Negative Out/RDL Clock Out TSB Time Slot Indicator(2) TSB Frame Sync TSB Multiframe Sync RSB Data Out RSB Signaling Out RSB Time Slot Indicator(2) RSB Frame Sync RSB Multiframe Sync Signaling Freeze CLAD Out (NC)(3) Test Data Out Digital CLADI REFCKI TCK TMS TDI Boundary Scan I = Input, O = Output, Interface Line Interface Transmitter Digital Receiver Transmit System Bus Receive System Bus Clock Rate Adapter (CLAD) CLAD In Reference Clock I 67 I 68 Test Clock I 53 Test Mode Select I 52 Test Data In I 55 PIO = Programmable I/O; controls located at PIO (address 018) (TSB) (RSB) (JTAG) (MPU) (RLIU, TLIU) (XMTR) (RCVR) Tx Clock Output Tx Positive Out/Tx NRZ Data(2) Tx Multiframe Sync |
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