BT8376EPF datasheet(38/323 Pages) CONEXANT

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2.0 Circuit Description

Bt8370/8375/8376

2.3 Jitter Attenuator

Fully Integrated T1/E1 Framer and Line Interface

2-10

Conexant

N8370DSE

2.3.1 Elastic Store

The elastic store size (RJAT or TJAT) is configurable using JSIZE[2:0] in the

JAT_CR. The elastic store sizes available are 8, 16, 32, 64, and 128 bits. The

32-bit elastic store depth is sufficient to meet jitter tolerance requirements in

cases where the jitter attenuator cutoff frequency is programmed at 6 Hz or below,

and when the selected clock reference is frequency-locked. The larger elastic

store depths allows greater accumulated phase offsets. For example, the 128-bit

depth can tolerate up to

±64 bits of accumulated phase offset.

Since the elastic store is a fixed size, it can overflow and under-run. Overflow

occurs when the elastic store is full; under-run occurs when the elastic store is

empty. If either of these two conditions occurs, the Jitter Attenuator Elastic Store

Limit Error bit (JERR) in the Error Interrupt Status register [ISR5; addr 006] is

set. To determine if an overflow or under-run occurs, the Jitter Attenuator

Empty/Full bit (JMPTY) must be read from the Receive LIU Status register

[RSTAT; addr 021].

The elastic store is a circular buffer with independent read and write pointers.

The difference between the read and write pointers is the phase error (JPHASE)

between the input and output clocks of the jitter attenuator and is used to generate

JCLK. The read and write pointers are initialized using JCENTER in the

JAT_CR. JCENTER resets the write pointer and forces the elastic store read

pointer to 1 half of the programmed JSIZE. JCENTER also resets the JMPTY

status, so JMPTY must be read before JCENTER is written.

If JDIR is configured to put the jitter attenuator in the receive path, the write

pointer is driven by the Receive Clock (RXCLK), and the read pointer is driven

by the dejittered recovered clock (JCLK). The dejittered recovered clock output is

available on the RCKO pin if the output is enabled using RCKO_OE in the

Programmable Output Enable register [POE; addr 019]. The dejittering of the

recovered clock is done by the Clock Rate Adapter Block (CLAD). CLAD is

described later in this document.

If JDIR is configured to put the jitter attenuator in the transmit path, the write

pointer is driven by the Transmit Clock (TXCLK), and the read pointer is driven

by the dejittered transmit clock (JCLK). TXCLK can be slaved to four different

clock sources: Transmit Clock Input (TCKI), Receive Clock Output (RCKO),

Receive System Bus Clock Input (RSBCKI), or Clock Rate Adapter Output

(CLADO). The dejittered transmit clock is available on the TCKO pin when the

output is enabled using TCKO_OE in POE.

The receive LIU input clock and data jitter tolerance meets TR 62411-1990, as

illustrated in Figure 2-7. The JAT input jitter tolerance is illustrated in Figure 2-9.

The JAT jitter transfer function meets TR 62411-1990, as defined in Figure 2-10

and Table 2-1.

BT8376EPF Datasheet(PDF) 38 Page - Synaptics Incorporated.

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