BT8376EPF datasheet(48/323 Pages) CONEXANT

48 / 323 page

2.0 Circuit Description

Bt8370/8375/8376

2.4 Receiver

Fully Integrated T1/E1 Framer and Line Interface

2-20

Conexant

N8370DSE

2.4.6 Test Pattern Receiver

The test pattern receiver circuitry can sync on framed or unframed PRBS patterns

and count bit errors. This feature is particularly useful for system diagnostics,

production testing, and test equipment applications. The PRBS patterns available

include 2E11-1, 2E15-1, 2E20-1, and 2E23-1. Each pattern can optionally

include Zero Code Suppression (ZCS).

The Receive Test Pattern Configuration register [RPATT; addr 041] controls

the test pattern receiver circuit. BSTART control bit (in RPATT) must be active to

enable the test pattern receiver and to begin counting bit errors. RPATT controls

the PRBS pattern, ZCS setting (ZLIMIT), and T1/E1 framing (FRAMED).

RPATT selects which PRBS pattern the receiver should hunt for pattern sync.

ZLIMIT selects the maximum number of consecutive zeros the pattern is allowed

to contain. FRAMED mode informs the PRBS pattern receiver not to search for

the pattern in the frame bit in T1 mode or search for the pattern in time slot 0 (and

time slot 16 if CAS framing is selected) in E1 mode. CAS framing is selected by

setting RFRAME[3] to 1 in the Primary Control register [CR0; addr 001]. If

FRAMED is disabled, the PRBS pattern receiver searches all time slots for the

test pattern.

The RESEED bit in RPATT informs the receive PRBS sync circuit to begin a

PRBS pattern search. Once the search begins, any additional writes to RESEED

restarts the pattern sync search at a different point in the pattern. The time to sync

depends on the pattern and number of bit errors in the pattern.

Pattern sync is reported (when found) in PSYNC status of the Pattern Interrupt

Status register [ISR0; addr 00B]. After pattern sync is found, the PRBS Pattern

Error counter [BERR; addr 058 and 059] begins counting bit errors detected on

the incoming pattern, provided that BSTART remains active. Error counting stops

if the BSTART bit is cleared. BERR counter is reset to 0 after every read, or

latched on every ONESEC interrupt as selected by LATCH_CNT [addr 046]. An

interrupt is available to indicate the BERR counter overflowed in ISR4.

BT8376EPF Datasheet(PDF) 48 Page - Synaptics Incorporated.