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TMS320C80GF Datasheet(PDF) 119 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 119 Page - Texas Instruments |
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119 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 116 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SDRAM read cycles Read cycles begin with an activate (ACTV) command to activate the bank and to select the row. The TC outputs the column address and activates the TRG / CAS strobe for each read command. For burst length 1 accesses, a read command can occur on each cycle. For burst-length 2 accesses, a read command can occur every two cycles. The TC places D[63:0] into the high-impedance state, allowing it to be driven by the memory, and latches input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. The CAS / DQM strobes are activated two cycles before input data is latched. If the second column in a burst is not required, then CAS / DQM is not activated. During peripheral device packet transfers, DBEN remains high (see Figure 94 through Figure 99). |
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