TMS320C80GF datasheet(115/171 Pages) TI

115 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

112

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SDRAM type cycles (continued)

Burst-length 1, 2 cycle latency reads, read

transfers, split-read transfers

CAS/DQM

Col A

Col B

Col C

Idle

Burst-length 1 writes, block writes, SRSs, write transfers,

split-write transfers

CAS/DQM

Col A

Col B

Col C

Idle

CAS/DQM

Col A

Col B

Col C

Idle

Burst-length 1, 3 cycle latency reads, read

transfers, split-read transfers

CAS/DQM

Col A, B

(B)

C (D)

Col C, D

Burst-length 2, writes

(F)

Col E, F

Idle

CAS/DQM

Col A, B

(B)

C (D)

Col C, D

Burst-length 2, 2 cycle latency reads, read transfers,

split-read transfers

(F)

Col E, F

Idle

CAS/DQM

Col A, B

(B)

C (D)

Col C, D

Burst-length 2, 3 cycle latency reads, read transfers,

split-read transfers

(F)

Col E, F

Idle

CAS/DQM

Col A

Col B

Burst-length 2, block writes, write transfers, split-write

transfers

Col C

Idle

CAS/DQM

Col A

Col B

Col C

Idle

Burst-length 1, 4 cycle latency reads, read

transfers,split-read transfers.

(B) C

CAS/DQM

Col A, B

Col C, D

Idle

Burst-length 2, 4 cycle latency reads, read

transfers,split-read transfers.

Col E, F

(D)

(F)

Figure 91. SDRAM Column Pipelines

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