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TMS320C80GF Datasheet(PDF) 116 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 116 Page - Texas Instruments |
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116 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 113 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 special SDRAM cycles To initialize the SDRAM properly, the TMS320C80 performs two special SDRAM cycles after reset. The ’C80 first performs a deactivate cycle on all banks (DCAB) and then initializes the SDRAM mode register with a mode register set (MRS) cycle. The CT code input at the start of the MRS cycle determines the burst length and latency that is programmed into the SDRAM mode register (see Figure 92 and Figure 93). |
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