AD4134 datasheet(38/92 Pages) AD

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Data Sheet

AD4134

CIRCUIT INFORMATION

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Rev. 0 | 38 of 92

Figure 70. Provide Master Clock to Multiple Devices from a Single Crystal

The XCLKOUT output is enabled by default in pin control mode

if the crystal clock options are selected. The XCLKOUT output is

disabled in pin control mode if the CMOS clock option is selected.

The XCLKOUT output is disabled by default in SPI control mode

and can be enabled by writing 1 to the XCLKOUT_EN bit.

POWER OPTIONS

Operating Power Modes

Depending on the bandwidth of interest for the measurement, the

AD4134 allows the user to trade measurement bandwidth with

power consumption or resolution through its two selectable power

modes: high performance and low power. The low power mode

operates with half the modulator clock frequency, resulting in com-

parable noise performance to the high performance mode at half

of the output data rate and 40% of power saving. For details of

the performance difference between the two modes, see the Noise

Performance and Resolution section.

Channel Power-Down

In SPI control mode, the four ADC channels can be individually

powered down to save power when not used.

The PWRDN_CHx bits control the power-down of each channel.

Powering down an ADC channel reduces the supply current and

the input current. The input of a powered down channel goes high-

Z. The reference input current reduces by 1/4 with the power-down

of each ADC channel.

Sleep Mode

Sleep mode can be activated in SPI control mode by setting the

SLEEP_MODE_EN bit to 1.

In this mode, the device powers down all the blocks except the

digital LDO regulator and it retains its on-chip register values.

The typical power consumption in this mode is 15 mW. The device

can resume full operation within 100 µs after exiting this mode.

Both the reference input and input channels go high-Z in

sleep mode.

Full Power-Down

The full power-down mode is activated by holding the PDN pin low.

All internal blocks are powered down in this mode.

The typical power consumption in this mode is 1 mW. The device

requires a power-up time of 10 ms after exiting this mode. After

exiting this mode, the device registers are reset to the default value.

Both the reference input and input channels go high-Z in

sleep mode.

RESET

When reset, the AD4134 restores the internal register values to the

default and resets the internal logics and functional blocks.

Two methods exist for the user to reset the AD4134: through a hard

reset by pulling the RESET pin low, or through a software reset by

writing 1 to SOFT_RESET (self clears).

ASYNCHRONOUS SAMPLE RATE

CONVERTER

One unique property of the CTSD modulator architecture is having

a fixed time constant. As a result, the AD4134 device operates at a

fixed modulator clock frequency.

To facilitate the accurate adjustment of the output data rate, the

AD4134 features a digitally programmable ASRC.

The ASRC is placed between the modulator and the digital filter of

each ADC channel. The ASRC has the following two inputs:

►

Data that comes at the MCLK rate from the modulator

►

ODR input, which is either an external asynchronous signal

(slave) or a fractional value (master)

Figure 71. Data Rate at Each Stage of Conversion Path

The digital PLL present in the ASRC block tracks and locks on

the ODR input and generates a fractional ratio. The ASRC works

through interpolation and resampling of the modulator output at a

fractional ratio to the sampling frequency of the modulator.

AD4134 Datasheet(PDF) 38 Page - Analog Devices

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