AD4134 datasheet(55/92 Pages) AD

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Data Sheet

AD4134

DEVICE CONFIGURATION

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Data Delay

The data output of each channel of the AD4134 can be individually

delayed by 0, 1, or 2 MCLK cycles using the MPC_CONFIG

amounts of phase delay depending on factors like gain setting and

filtering. This feature gives the user flexibility to match the delays

on different channels and thus achieving tight phase matching

between channels.

POWER MODES

The AD4134 offers two power modes, high performance mode and

low power mode. These modes are available in both pin control

mode and SPI control mode. In pin control mode, the PWRMODE/

GPIO3 pin controls the AD4134 operating power mode. In SPI

control mode, the POWER_MODE bit controls the power mode.

Additional sleep mode is available in SPI control mode. Table 34

summarizes the power mode configurations. In both pin control

mode and SPI control mode, a full device power-down can be

initiated through the pin.

Table 34. Power Mode Configuration

PWRMODE/GPIO3 or

POWER_MODE Bit

SLEEP_MODE_EN

Device Power Mode

Low power mode

High performance mode

Sleep mode

To operate the device correctly in low power mode, the user must

toggle the setting from low power mode to high performance mode

and back to low power mode.

In pin control mode, to set the AD4134 in low power mode, toggle

the PWRMODE/GPIO3 pin to high and after a delay of 10 ms

toggle it back to low. In SPI control mode after power-up, change

the POWER_MODE bit from low to high and after a delay of 10 ms

change it back to low.

Also, in pin slave mode, first provide the ODR signal and then

change the power mode to ensure dynamic sampling of the

PWRMODE/GPIO3 pin.

INHERENT ANTIALIASING FILTER MODES

The CTSD architecture allows the AD4134 to reject signals around

the integer multiples of the modulator sampling frequency, protect-

ing its input band of interest from aliasing. The AD4134 offers two

antialiasing modes. The default antialiasing mode, AA1, offers a

typical 85 dB of aliasing rejection.

The other antialiasing mode, AA2, improves the rejection to 102.5

dB with the cost of a higher offset drift of 1.03 µV/°C, additional

power consumption of 3 mW per channel, and higher noise level

with dynamic range reduction.

The AA2 mode is only available in SPI control mode and can be

enabled by setting the AA_MODE bit to 1.

Table 35 shows typical performance differences in inherent antialias

modes. The filter is wideband 0.433 × ODR FIR filter, and the ODR

value is ODR = 374 kSPS.

Table 35. Performance Difference in Inherent Antialias Modes

Parameter

AA1 Mode

AA2 Mode

Dynamic Range

107.4 dB

105.9 dB

SNR

106.6 dB

105.4 dB

Alias Rejection

85 dB

102.5 dB

Offset Drift

0.5 µV/°C

1.03 µV/°C

Power per Channel

126 mW

129 mW

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